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About On-Chip Networks
With the ability to integrate a large number of cores on a single chip, research into on-chip networks to facilitate communication becomes increasingly important. On-chip networks seek to provide a scalable and high-bandwidth communication substrate for multi-core and many-core architectures. High bandwidth and low latency within the on-chip network must be achieved while fitting within tight area and power budgets. In this lecture, we examine various fundamental aspects of on-chip network design and provide the reader with an overview of the current state-of-the-art research in this field. Table of Contents: Introduction / Interface with System Architecture / Topology / Routing / Flow Control / Router Microarchitecture / Conclusions
Detailed Information
| Author: | Li-Shiuan Peh, Natalie Enright Jerger |
|---|---|
| Publication Year: | 2009 |
| ISBN: | 9781598295856 |
| Pages: | 141 |
| Language: | English |
| File Size: | 2.415 |
| Format: | |
| Price: | FREE |
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