Table Of ContentElectrical Engineering
NONVOLATILE MEMORY DESIGN
MAGNETIC, RESISTIVE, AND PHASE CHANGE N
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As complementary metal-oxide semiconductor (CMOS) integration technology enters the nano era,
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unprecedented growth in traditional nonvolatile memory technologies—such as SRAM, DRAM, and A
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Flash—is creating severe technical barriers and rising production costs not seen in 40 years.
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Nonvolatile Memory Design: Magnetic, Resistive, and Phase Change explores the latest insights E
and subsequent developments for solving a wide range of problems. These include slowed/limited
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technological scaling and programming speed, large process and device variation, high leakage
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power, increasingly complex manufacturing processes, and reliability. M
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Written by two renowned engineering professors working at the cutting edge of this quickly evolving
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field, the book reflects their specialized experience as it explores new alternative memory technologies.
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In particular, it introduces a new concept known as universal memory and discusses the emerging E
technologies that are close to meeting its requirements. Universal memory technology could offer S
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several attractive characteristics, including high density (low cost), high speed (for both read and write G
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operations), low power (both leakage and dynamic powers), random accessibility, non volatility, and
unlimited endurance to meet the requirements of applications ranging from supercomputers to M
handheld devices. A
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An invaluable informational tool for semiconductor memory designers, students, and many E MAGNETIC, RESISTIVE, AND PHASE CHANGE
others, this book covers T
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• Background and fundamental mechanisms of emerging nonvolatile memory technologies R
(i.e., physics, device structure, materials, and operating mechanisms) E
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• Manufacture and process technologies (such as those used for special storage devices
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and CMOS integration technology)
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• Circuit design techniques (i.e., memory array design, read/write circuitry, and testing strategies) I
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• Potential applications and future trends E
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Phase change memory and toggle-mode magnetic random access memory are potential technologies N
already on the market. Other candidates—such as spin�torque transfer RAM and resistive RAM—are D
still in the research stage but have demonstrated very promising characteristics. Most major semicon- P
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ductor and storage companies are investing tens of billions of dollars to find a winner—and the
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race is on. S
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K10380 N
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ISBN: 978-1-4398-0745-3 E
90000
9 781439 807453
MAGNETIC, RESISTIVE, AND PHASE CHANGE
MAGNETIC, RESISTIVE, AND PHASE CHANGE
Boca Raton London New York
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Contents
Preface.......................................................................................................................ix
Author.Biographies..............................................................................................xiii
. 1. Introduction to Semiconductor Memories.................................................1
1.1. Classification.and.Characterization.of.Semiconductor.
Memories................................................................................................1
1.1.1. Read‑Only.Memory..................................................................1
1.1.2. Erasable.Programmable.ROM.and.Flash.Memory..............4
1.1.3. Electrically.Erasable.Programmable.ROM............................4
1.1.4. Static.RAM.................................................................................5
1.1.5. Dynamic.RAM..........................................................................7
1.1.6. Nonvolatile.Memories..............................................................9
1.1.6.1 Phase.Change.Memory..........................................10
1.1.6.2 Magnetic.Random.Access.Memories...................10
1.1.6.3 Resistive.RAM.........................................................11
1.1.6.4 Memristor.................................................................11
1.2. Devices...................................................................................................12
1.2.1. MOSFET...................................................................................12
1.2.1.1 Cutoff.Regions.........................................................14
1.2.1.2 Triode.Region...........................................................14
1.2.1.3 Saturation.Region....................................................15
1.2.2. Diode.........................................................................................16
1.2.3. Passive.Component.................................................................17
1.2.3.1 Capacitor...................................................................17
1.2.3.2 Resistor......................................................................17
1.3. Designing.Memory.and.Array.Structures.......................................18
1.3.1. Memory.Architecture.and.Building.Blocks........................18
1.3.1.1 Memory.Cell.Array.................................................18
1.3.1.2 I/O.Interface.............................................................20
1.3.2. Memory.Peripheral.Circuitry................................................21
1.3.2.1 Decoder.....................................................................21
1.3.2.2 Sense.Amplifier.......................................................22
1.3.2.3 Write.Driver.............................................................23
1.3.3. Memory.Reliability.and.Yield...............................................25
1.3.3.1 Reliability.................................................................25
1.3.3.2 Yield...........................................................................25
1.3.4. Testing......................................................................................27
References........................................................................................................29
v
vi Contents
. 2. Phase Change Memory.................................................................................31
2.1. Introduction.to.PCM............................................................................31
2.1.1. Phase.Change.Properties.......................................................31
2.1.2. History.of.PCM.......................................................................31
2.1.3. Phase.Change.Operation.......................................................32
2.2. Material.Research................................................................................35
2.2.1. Ge SbTe .Alloys......................................................................35
2 2 5
2.2.2. Doped.GST...............................................................................35
2.2.3. GeSb.Material..........................................................................38
2.3. Device.Research...................................................................................38
2.3.1. Bridge.Cell................................................................................38
2.3.2. Pillar.Cell.................................................................................39
2.3.3. Pore.Cell...................................................................................41
2.4. Electrothermal.Modeling....................................................................44
2.4.1. PCM.Design.Technique.........................................................46
2.4.1.1 Access.Device.of.PCM.Bit.Cell..............................46
2.4.1.2 Multilevel.Cell.........................................................52
2.4.2. Program.Algorithm................................................................55
2.4.3. Read.and.Other.Peripheral.Circuitry...................................57
2.4.4. Physical.Limit.of.PCM...........................................................59
2.4.4.1 Bit.Retention.............................................................60
2.4.4.2 Bit.Endurance...........................................................63
2.4.4.3 Continue.Moore’s.Law............................................63
References........................................................................................................64
. 3. Spin‑Transfer Torque RAM.........................................................................69
3.1. Introduction.of.Spin‑Transfer.Torque.Technology..........................69
3.1.1. Spin‑Transfer.Torque.Theory................................................69
3.1.2. Dynamic.Behavior.of.an.MTJ...............................................71
3.1.3. Some.Important.Parameters.of.MTJ....................................73
3.1.3.1 R ,.R ,.R ,.and.Tunneling.Magnetoresistance....73
H. L. AP.
3.1.3.2 Aspect.Ratio.............................................................73
3.1.3.3 Resistance‑Area.Product........................................73
3.1.3.4 Switching.Current.I ...............................................74
C
3.1.3.5 MTJ.Switching.Probability.P ..............................75
sw
3.2. Spin‑Transfer.Torque.Random.Access.Memory..............................76
3.2.1. Basic.Structure.........................................................................76
3.2.2. Write.and.Read.Mechanism..................................................77
3.3. STT‑RAM.Architecture.......................................................................78
3.4. STT‑RAM.Modeling.............................................................................79
3.4.1. Dynamic.MTJ.Modeling........................................................79
3.4.2. Cell.Modeling..........................................................................79
3.5. Design.Challenges...............................................................................81
3.5.1. Sources.of.Process.Variations................................................81
3.5.1.1 CMOS.Process.Variations......................................81
Contents vii
3.5.1.2 MTJ.Resistance.Variations.....................................81
3.5.1.3 Switching.Current.Variations................................81
3.5.2. Static.Failures.in.STT‑RAM...................................................83
3.6. Design.Techniques.of.STT‑RAM........................................................84
3.6.1. STT‑RAM.Cell..........................................................................84
3.6.1.1 Other.STT‑RAM.Cell.Designs...............................84
3.6.1.2 STT‑RAM.Cell.Scalability......................................88
3.6.1.3 Variation.Control.of.STT‑RAM.Bit.Cell................90
3.6.2. STT‑RAM.Circuit.Design—Self‑Reference.Scheme...........90
3.6.2.1 Conventional.Sensing.Scheme..............................90
3.6.2.2 Conventional.Self‑Reference.Sensing.Scheme......92
3.6.2.3 Nondestructive.Self‑Reference.Sensing.Scheme...93
3.6.2.4 Voltage‑Driven.Nondestructive.
Self‑Reference.Sensing.Scheme.............................95
3.6.2.5 Comparison.of.Different.Sensing.Schemes.........97
3.6.3. STT‑RAM.Architecture.Design.Technique.........................98
3.6.3.1 Read‑Before‑Write.Scheme.....................................98
3.6.3.2 Early.Write.Termination.........................................99
3.6.3.3 Data.Inverting........................................................101
3.6.3.4 Wear.Leveling........................................................101
3.6.3.5 Dual.Write‑Speed.Method...................................102
3.7. Multilevel.Cell....................................................................................104
3.7.1. Write.Scheme.for.Multilevel.Cells......................................106
3.7.1.1 Simple.Write.Scheme.of.MLC.STT‑RAM.Cells....107
3.7.1.2 Complex.Write.Scheme.of.MLC.STT‑RAM.
Cells.........................................................................108
3.7.1.3 Hybrid.Write.Scheme.of.MLC.STT‑RAM.Cells...108
3.7.2. Sensing.Scheme.for.MLC.....................................................109
References......................................................................................................110
. 4. Resistive Random Access Memory..........................................................115
4.1 Variety.of.R‑RAM...............................................................................115
4.1.1. Electrochemical.Metallization.Devices.............................115
4.1.2. Valence.Change.System.......................................................117
4.2 R‑RAM.Operations............................................................................119
4.3 Single.Cell.R‑RAM.Design...............................................................120
4.3.1. Crossbar.Structure.Design.without.Switching.Device...120
4.3.2. R‑RAM.Cell.Design.with.Active.Switching.Device.........121
4.3.3. R‑RAM.Cell.Design.with.Passive.Switching.Device.......122
4.4 R‑RAM.Scalability..............................................................................124
4.4.1. Basic.Memory.Structure.and.Its.Fabrication.....................124
4.4.2. Statistics.of.RSD.Resistance.................................................125
4.4.3. Electrical.Properties.............................................................128
4.5 R‑RAM.Array.Structure....................................................................130
4.5.1. Conventional.Crossbar.Array.............................................130
4.5.2. Complementary.Crossbar.Structure..................................132
viii Contents
4.6 3D.Stacking.R‑RAM...........................................................................134
4.6.1. 3D.Unipolar.R‑RAM.Design...............................................136
4.6.2. 3D.Bipolar.R‑RAM.Design..................................................137
4.6.3. 3D.High‑Density.Interleaved.Memory.Design................138
4.6.3.1 Read.Operation......................................................141
4.6.3.2 Write.Operation.....................................................141
4.6.3.3 Impact.of.Data.Patterns........................................142
4.6.3.4 Impact.of.Cell.Location........................................144
4.7 Summary.and.Future........................................................................146
References......................................................................................................147
. 5. Memristors....................................................................................................151
5.1. Memristor.Theory..............................................................................151
5.2. Metal‑Oxide.Memristor....................................................................153
5.2.1. Titanium.Dioxide.as.Memristor.........................................153
5.2.2. Other.Oxide‑Based.Memristor.Options............................156
5.3. Spintronic.Memristor........................................................................156
5.3.1. Spintronic.Device.as.Memristor.........................................156
5.3.2. Compact.Model.of.Spintronic.Memristor.........................159
5.3.2.1 Model.of.Spintronic.Memristor...........................159
5.3.2.2 Electrical.Property.of.Spintronic.Memristor.....160
5.3.2.3 Model.Summary....................................................162
5.3.3. I‑V.Curve.and.Frequency.Response...................................162
5.3.3.1 M‑q.Curve..............................................................162
5.3.3.2 Sinusoidal.Wave.Excitation..................................164
5.3.3.3 Biased.Sinusoidal.Wave.Excitation.....................164
5.4. Applications.and.Future.Trends......................................................166
5.4.1. Memristor.Memory..............................................................166
5.4.2. Memristor.Thermal.Sensor.................................................170
References......................................................................................................174
. 6. The Future of Nonvolatile Memory.........................................................177
6.1. Developments.in.Future.Nonvolatile.Memory.Technologies.....177
6.1.1. Review.of.Current.Efforts.in.the.World.............................177
6.2. Future.Research.Trends....................................................................180
6.2.1. Who.Will.Be.the.Winner?....................................................181
6.2.2. Semiconductor.Memory.Roadmap....................................181
6.2.3. Forecast...................................................................................181
References......................................................................................................182
Preface
Among.the.numerous.exciting.inventions.that.dramatically.changed.our.
everyday.life.in.the.20th.century,.semiconductor.technology.is.one.of.the.
most.influential.achievements..In.1970,.the.first.two.important.embodi‑
ments.of.semiconductor.memory—1‑kilobyte.(KB).dynamic.random.access.
memory.(DRAM).and.256‑KB.static.random.access.memory.(SRAM)—were.
invented.by.Intel/IBM.and.Fairchild,.respectively..Because.both.DRAM.and.
STRAM.require.power.to.maintain.the.stored.information,.they.are.catego‑
rized.as.volatile memory.
Another.category.of.semiconductor.memory.is.called.nonvolatile memory,.
which.can.keep.information.stored.even.when.power.is.disabled..One.example.
of.nonvolatile.memory.is.flash memory,.which.is.based.on.electrically.erasable.
programmable.read‑only.memory.(EEPROM).technology..The.first.commer‑
cial.EEPROM.product.was.introduced.by.Intel.in.1983,.with.a.16‑KB.capacity.
The. capacity. of. semiconductor. memory. has. achieved. unprecedented.
increase:.the.latest.flash.memory.capacities.have.reached.512.gigabytes.(GB)..
This.means.that.flash.memory.capacity.has.doubled.every.12.months.con‑
tinuously.for.25.years..The.cost.per.bit.of.flash.memory.was.also.reduced.
by.almost.200,000.times..Driven.by.the.ever‑exploding.demand.for.higher.
capacity.nonvolatile.memory.in.pervasive.computing.and.communication.
devices,.flash.memories.have.been.the.fastest.growing.segment.in.the.global.
semiconductor.industry:.in.2007,.the.total.capacity.of.flash.memory.shipped.
to.market.exceeded.DRAM.
As.complementary.metal‑oxide.semiconductor.(CMOS).integration.tech‑
nology.enters.the.nano.regime,.engineers.are.facing.technology.challenges.
unlike.any.encountered.in.the.40‑year.history.of.the.semiconductor.industry:.
large.process.and.device.variation,.high.leakage.power,.complex.manufac‑
turing.processes,.etc..These.challenges.not.only.slow.down.the.technology.
scaling.(Moore’s.law).but.also.introduce.significant.reliability.issues..For.
example,.one.fundamental.limitation.of.flash.memory.is.called.endurance,.
which.is.measured.by.the.number.of.times.the.flash.memory.cell.can.be.
programmed..When.process.technology.scales.down.to.45.nm.and.beyond,.
the.endurance.of.a.multilevel.flash.memory.cell.is.degraded.to.about.1,000.
cycles..Very.low.endurance.introduces.high.management.costs.for.memory.
operation.and.severely.limits.the.application.of.flash.memory.
Another.technical.limitation.of.flash.memory.is.the.slow.programming.
(writing).speed..Usually.it.takes.up.to.200.ms.to.program.one.flash.memory.
cell..An.intelligent.control.scheme.like.program–verify–reprogram.….is.usu‑
ally.used.to.overcome.the.instability.of.flash.memory.cells.due.to.process.
variation,.etc..However,.such.a.complex.scheme.may.take.up.to.1.ms.in.order.
to.successfully.write.one.bit..Slow.programming.speed.significantly.limits.
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