Nanometer CMOS Sigma-Delta Modulators for Software Defined Radio

297 Pages·2012·23.05 MB·English

by  Alonso Morgado

Nanometer CMOS Sigma-Delta Modulators
for Software Defined Radio
Alonso Morgado • Rocío del Río
José M. de la Rosa
Nanometer CMOS
Sigma-Delta Modulators
for Software Defined Radio
2123
AlonsoMorgado JoséM.delaRosa
InstitutodeMicroelectrónicadeSevilla InstitutodeMicroelectrónicadeSevilla
CentroNacionaldeMicroelectrónica CentroNacionaldeMicroelectrónica
IMSE-CNM(CSIC/UniversidaddeSevilla) IMSE-CNM(CSIC/UniversidaddeSevilla)
ParqueTecnológicodelaCartuja ParqueTecnológicodelaCartuja
C/AméricoVespucios/n C/AméricoVespucios/n
Sevilla,Spain Sevilla,Spain
[email protected] [email protected]
RocíodelRío
InstitutodeMicroelectrónicadeSevilla
CentroNacionaldeMicroelectrónica
IMSE-CNM(CSIC/UniversidaddeSevilla)
ParqueTecnológicodelaCartuja
C/AméricoVespucios/n
Sevilla,Spain
[email protected]
ISBN978-1-4614-0036-3 e-ISBN978-1-4614-0037-0
DOI10.1007/978-1-4614-0037-0
SpringerNewYorkDordrechtHeidelbergLondon
LibraryofCongressControlNumber: 2011933912
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Preface
Thisbookrepresentsacontributiontothedesignofsigma-delta((cid:2)(cid:3))modulators
intendedfortheA/Dconversioninmulti-standardmulti-modewirelesstransceivers,
implementedinnanometerCMOStechnologies.Inthesetransceivers,ADCsarekey
partsbecausetheyneedtooperatewithawidespreadoftheirspecifications;namely,
effective resolution and signal bandwidth. (cid:2)(cid:3) modulators are very suited for the
implementation of reconfigurableADCs in highly integrated transceivers. On the
one hand, the key principles of (cid:2)(cid:3) modulators (oversampling and noise shaping)
determinethedynamicrangeoftheADC,sothattheiradjustmentcontributestoadapt
theconverterperformancetodifferentspecificationswithlargehardwarereuse.On
the other, both principles make them robust with respect to non-idealities of an
integratedimplementation.
In spite of the advantages mentioned above, the design of nanometer CMOS
(cid:2)(cid:3)ADCsisnoteasy,speciallywhenconsideringadaptabilityandreconfigurability
features.Itinvolvesanumberofpracticalissuesandtrade-offsatbotharchitectural
and circuit level that must be taken into account for optimizing performance in
termsofpowerdissipation(deviceportabilityandautonomy),siliconarea(cost)and
time-to-marketdeployment.
Inthiscontext,theworkinthisbookpresentsinnovativesolutionsfortheimple-
mentation of flexible (cid:2)(cid:3) modulators intended for the next generation of wireless
hand-heldmobileterminals,implementedasaSoCinnanometerCMOSprocesses.
Novel adaptive and reconfigurable (cid:2)(cid:3) modulator topologies—based on the com-
bination of resonation, unity signal transfer function, and a new type of cascade
withextrainter-stagefeedbackloopsandsimplifieddigitalcancellationlogic—are
presented.Thesestrategiesallowtoreducetherequirementsoftheembeddedam-
plifiersintermsoffiniteDCgain,non-linearityandoutputswing.Thismakesthem
very suited for the implementation of low-voltage low-power widebandADCs.At
thecircuitlevel,differentstrategiesareappliedtoadapttheperformanceofthe(cid:2)(cid:3)
modulatorstothedifferentsetsofspecificationswithadaptablepowerconsumption.
A number of architectures, circuit techniques and design procedures presented
inthisbookaredemonstratedthroughthedesign,implementationandexperimental
characterization of three IC prototypes. The first one—implemented in a 130-nm
CMOS technology—consists of an expandable cascade topology that comprises
vii
viii Preface
a 2nd-order front-end stage followed by 1st-order stages, with the last one be-
ingswitchableandalsoincorporatingmulti-bitquantization.Thechipreconfigures
the modulator loop filter order, the sampling frequency and the number of bits of
the internal (back-end) quantizer, and scales the power consumption of internal
building blocks in order to adapt the performance to the specifications of 2G/3G
standards,consideringadirectconversionreceiver.Measurementresultsshowacor-
rectoperationforGSM/Bluetooth/WCDMAstandards,featuringadynamicrangeof
86.7/81.0/63.3dBforsignalbandwidthsof200kHz/1MHz/4MHz,respectively.The
powerconsumptionis25.2/25.0/44.5mW,ofwhich11.0/10.5/24.8mWcorresponds
totheanalogpartofthecircuit.
Thesecondchip—implementedina90-nmCMOSprocess—consistsofatwo-
stage(2–2)topologywith3-levelquantizationandunitysignaltransferfunctionin
bothstages.Thechipreconfiguresitsloopfilter,clockfrequencyandscalespower
according to the required specifications for different standards included in B3G
wireless telecom, covering: GSM, Bluetooth, GPS, UMTS, DVB-H andWiMAX.
Measurement results feature a dynamic range of 78/70/71.5/66/62/52dB within
bandwidths of 100 kHz/500 kHz/1MHz/2MHz/4MHz/10MHz, while consuming
4.6/5.35/6.2/8/8/11mW,respectively.
Thethirdchipisa2-2-2cascademadeupofunity-STFstages. Similarlytothe
secondchip,a1.2-V90-nmCMOStechnologyisemployed.Thechipcanreconfig-
ureitsloopfilteringorderfrom6to4or2byswitchingoffoneortwostagesinthe
cascade,respectively.Thequantizationineachstagecanbeselectedto3or5levels.
Every stage can work concurrently or as part of a cascade, so this (cid:2)(cid:3) modulator
canprocessuptothreestandardsinparallel.Theemployedarchitectureincorporates
programmableresonationinthelasttwostages.Thebiascurrentsofmainmodulator
buildingblocksareadjustableon-chip.Also,thesamplingfrequencycanbeadapted
to the requirements of each operation mode. Experimental characterization of this
chipindicatesacorrectoperationformostofthereconfigurationtechniquesimple-
mented; namely, adaptation of the in-loop filtering order, programmability of the
biascurrentsinthemodulatorbuildingblocks,variationoftheinternalquantization
andconcurrency.
Theworkinthisbookdemonstratesthefeasibilityofusing(cid:2)(cid:3)modulatorsfor
theefficientimplementationofmulti-standardtelecomsystemsandshowstheway
forthepracticaldeploymentofthesoftwaredefinedradioparadigm.
Sevilla AlonsoMorgado
March2011 RocíodelRío
JoséM.delaRosa
Acknowledgments
TheauthorswouldliketoexpresstheirgratitudetoProf.ÁngelRodríguez-Vázquez,
Prof.BelénPérez-Verdú,Dr.FernandoMedeiro(IMSE-CNM,CSIC/Universityof
Sevilla),Prof.MauritsOrtmanns(UniversityofUlm),Dr.AnaRusu(RoyalInstitute
ofTechnology, KTH, Stockholm), Dr. GeertVan der Plas and Dr. Julien Ryckaert
(IMEC,Leuven),forthereviewofthistext.Specially,theauthorswishtothankDr.
GeertVanderPlasandDr.JulienRyckaertfortheirvaluableinputsandhelpinthe
design of the second chip presented in Chap. 5 of this book, and also to Mr. José
G. García-Sánchez, Mr. Luis I. Guerrero-Linares and Mr. SohailAsghar for their
supportwiththedesignandlayoutofthethirdprototypedescribedinChap.6.
This work was supported in part by the Spanish Ministry of Innovation and
Science(withsupportfromtheEuropeanRegionalDevelopmentFund)underCon-
tractTEC2007-67247-C02-01/MICandContractTEC2010-14285/MIC,andinpart
by the Regional Ministry of Innovation, Science and Enterprise under Contract
TIC-2532.
ix
Table of Contents
1 Introduction................................................... 1
1.1 OverviewofWirelessStandardsandMobileSystems............. 4
1.1.1 Towards4GMobileTerminals ......................... 5
1.1.2 CircuitsandSystemsfor4G:Challenges
andInnovations...................................... 8
1.2 Multi-StandardWirelessTransceivers.......................... 10
1.3 FlexibleCMOSAnalogBasebandCircuitsfor4GTelecom........ 14
1.3.1 ChannelSelection.................................... 15
1.3.2 ProgrammableBasebandFiltering ...................... 16
1.4 ReconfigurableADCsforSDR-BasedMobileTerminals .......... 17
2 (cid:2)(cid:3)ADCs:BasicConcepts,TopologiesandStateoftheArt ......... 23
2.1 FundamentalsoftheA/DConversion .......................... 24
2.1.1 Sampling ........................................... 25
2.1.2 Quantization ........................................ 25
2.1.3 WhiteNoiseApproximationofQuantizationError......... 26
2.1.4 Oversampling ....................................... 27
2.1.5 QuantizationNoiseShaping ........................... 28
2.2 Basicsof(cid:2)(cid:3)A/DConverters ................................ 29
2.2.1 SignalProcessingina(cid:2)(cid:3)Modulator ................... 31
2.2.2 PerformanceMetricsof(cid:2)(cid:3)Modulators................. 32
2.2.3 IdealPerformanceof(cid:2)(cid:3)Modulators ................... 34
2.3 Classificationof(cid:2)(cid:3)Modulators.............................. 35
2.4 Single-Loop(cid:2)(cid:3)Architectures ............................... 35
2.4.1 Second-Order(cid:2)(cid:3)Modulator .......................... 36
2.4.2 High-Order(cid:2)(cid:3)Modulators ........................... 37
2.5 Cascade(cid:2)(cid:3)Architectures................................... 42
2.6 Multi-bit(cid:2)(cid:3)Architectures .................................. 47
2.6.1 ImpactofDACNon-linearities ......................... 47
2.6.2 DynamicElementMatching ........................... 49
2.6.3 Dual-QuantizationTechniques ......................... 50
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xii TableofContents
2.7 StateoftheArtin(cid:2)(cid:3)ADCs ................................. 54
2.8 Summary ................................................. 57
3 New(cid:2)(cid:3)CascadeModulatorsfortheNextGeneration
ofWirelessTelecom ............................................ 59
3.1 StrategiesforEfficientCascade(cid:2)(cid:3)MsinMulti-Mode
Applications ............................................... 59
3.1.1 ModulatorOrderReconfigurationandConcurrency........ 60
3.1.2 ExpandableCascade(cid:2)(cid:3)Ms ........................... 62
3.1.3 Unity-STFCascadeArchitectures....................... 65
3.1.4 PreviouslyReportedResonation-Based(cid:2)(cid:3)Ms ........... 69
3.1.5 SMASHArchitectures ................................ 72
3.2 NovelCascadeArchitecturesBasedonPreviousStrategies ........ 74
3.2.1 ProposedResonation-BasedArchitectures................ 75
3.2.2 NovelUnity-STFSMASH-BasedArchitecture............ 86
3.2.3 NovelSMASH(cid:2)(cid:3)MswithResonation ................. 92
3.3 PracticalTimingIssuesoftheNovelArchitectures ............... 97
3.3.1 ImplementationandTimingofUSTF(cid:2)(cid:3)Ms............. 98
3.3.2 TimingProblemsinUnity-STFCascade(cid:2)(cid:3)Ms .......... 101
3.3.3 AlternativeSMASH-andResonation-Based
Architectures ........................................ 103
3.4 Summary ................................................. 108
4 A130-nmCMOSReconfigurable2-1-1CascadeSC(cid:2)(cid:3)M
forGSM/BT/UMTS ............................................ 111
4.1 ReceiverConsiderationsandADCSpecifications ................ 112
4.2 SelectionoftheModulatorArchitecture ........................ 115
4.2.1 Expandable(cid:2)(cid:3)CascadeArchitecture................... 116
4.2.2 Explorationof(cid:2)(cid:3)CascadeCandidates ................. 117
4.2.3 FinalModulatorArchitectureSelection .................. 121
4.3 SCImplementationoftheReconfigurable(cid:2)(cid:3)Modulator......... 122
4.4 ElectricalDesignoftheModulatorBlocks...................... 126
4.4.1 Amplifiers .......................................... 126
4.4.2 Capacitors .......................................... 128
4.4.3 Switches............................................ 130
4.4.4 Comparators ........................................ 131
4.4.5 Multi-bitQuantizer................................... 132
4.4.6 AuxiliaryBlocks..................................... 133
4.4.7 CompleteModulatorSimulationResults ................. 139
4.5 LayoutandAreaDistribution................................. 141
4.6 ExperimentalResults ....................................... 143
4.7 Summary ................................................. 149