Nanometer CMOS ICs: From basics to ASICs

754 Pages·2008·21.828 MB·English

by  Dr. Ir. H. J. M. Veendrick (auth.)

Nanometer CMOS ICs
Nanometer CMOS ICs
From basics to ASICs
Harry Veendrick
~
Springer
the languag of sci nee
mybusinessmedia
Nanometer CMOS ICs
Author:
Dr. Ir. H.J.M.Veendrick
NXP Semiconductors-Research
E-mail: [email protected]
Cover design: Bram Veendrick
Photographs used in cover: NXP Semiconductors
Typesetting and layout: Harold Benten and Dre van den Elshout
Illustrations: Kim Veendrick and Henny Alblas
First English edition: 2008
This book is based on various previous publications. The first original 1990 pub
lication (Delta Press b.v.) was in the Dutch language. In 1992 a revised, updated
and translated English edition of that book was jointly published by VCR Verlags
gesellschaft (Weinheim, Germany) and VCR Publishers Inc. (NY, USA). The third
book, entitled Deep-Submicron CMOS ICs: from Basics to ASICs, was a joint pub
lication of Ten Ragen en Starn, Deventer, The Netherlands, and Kluwer Academic
Publishers, Boston, USA) and published in two editions (1998and 2000).
This new book covers the same subjects, but then they are completely revised and
updated with the most recent state-of-the-art material. It coversallsubjects,related
to nanometer CMOS ICs: physics,technologies,design, testing,packagingand failure
analysis. The contents have increased by almost one third, leading to a much more
detailed and complete description of most ofthe subjects. This new book is almost
full colour.
ISBN 978-1-4020-8332-7 NUR 950
© 2008 Springer, Heidelberg, New York, Tokyo
Mybusinessmedia, Deventer, The Netherlands
All rights reserved. No part of this book may bereproduced,stored in a database or
retrievalsystem,or published, inany formor inany way,electronically,mechanically,
by print,photo print,microfilm or anyother means without prior written permission
from the publisher. Information published in this work, in any form,may be subject
to patent rights and is intended for study purposes and private useonly.
Although this book and its contents were produced with great care, neither the au
thor nor the publisher can guarantee that the information contained therein is free
from errors. Readers are advised to keep in mind that statements, data, illustra
tions, proceduraldetailsor other items may inadvertently contain inaccuracies. This
book contains many sources and references of text, photographs and illustrations.
Although the author has given a lot of attention to carefully refer to the source of
related material, he already apologizes for the one or few individual occasions that
this has slipped his final review.
Foreword
CMOS scaling isnowenteringthe deca-nanometerera. This enablesthe design
of systems-on-a-chip containing more than 10 billion transistors. However,
nanometer level device physics also causes a plethora of new challenges that
percolate all the way up to the system level.
Therefore system-on-a-chip design is essentially teamwork requiring a close
dialogue between system designers, software engineers, chip architects, intel
lectual property providers, and process and device engineers. This is hardly
possible without a common understanding of the nanometer CMOS medium,
its terminology, its future opportunities and possible pitfalls. This iswhat this
book provides.
It is a greatly extended and revised version ofthe previous edition that was
addressing deep-submicron CMOS systems. So besides the excellent coverage
ofall basicaspectsofMOS devices,circuitsand systems it leads the reader into
the novelintricacies resulting from scaling CMOS down to the deca-nanometer
level. New in this edition is the attention to the issues of increased leakage
power and its mitigation, to strain induced mobility enhancement and to sub
45nm lithographic techniques. Immersion and double patterning litho the use
of high index fluids as well as of extreme UV and other alternative litho ap
proaches for sub 32nm are extensively discussed together with their impact
on circuit layout. The design section now also extensively covers design tech
niques for improved robustness, yield and manufacturing in view of increased
device variability, soft errors and decreased reliability when reaching atomic
dimensions. In the packaging section attention is paid to rapidly emerging 3D
integrationtechniques. Finallytheauthorshareshisthoughts onthe challenges
of further scaling when approaching the end of the CMOS roadmap by 2015.
This book isunique in that it coversina very comprehensivewayallaspects
ofthe trajectory from process technology to thedesign and packaging ofrobust
and testable systems in nanometer scale CMOS.
It is the reflection of the author's own research in this domain but also of
almost 30years experience in interactiveteachingofCMOS design to NXP and
PHILIPS system designers and process engineers alike. It providescontext and
perspective to both sides.
I strongly recommend this book to all engineers involved in the design and
manufacturingoffuture systems-on-silicon as wellas to engineeringundergrad
uates who want to understand the basics that make electronics systems work.
Leuven, February 2008
Hugo De Man
Professor Emeritus K.U. Leuven
Senior FellowIMEC
Leuven
Belgium
v
Preface
An integrated circuit (IC) isa pieceofsemiconductor material,on which
a number of electronic components are interconnected. These intercon
nected 'chip' components implement a specific function. The semicon
ductor material is usually silicon but alternatives include gallium ar
senide.
ICs are essentialinmost modern electronic products. Thefirst IC was
created by Jack Kilby in 1959. Photographs of this device and the in
ventor are shown in figure 3. Figure 1illustrates thesubsequent progress
in IC complexity. This figure shows the numbers of components for ad
vanced ICs and the year in which these ICs were first presented. This
doubling in complexity every two years was predicted by Moore (Intel
1964), who's law is still valid today for the number of logic transistors
on a chip. However, due to reaching the limits ofscaling, the complexity
doubling of certain memories now happens at a three-year cycle. This
is shown by the complexity growth line which is slowly saturating.
Figure 2 shows the relative semiconductor revenue per IC category.
CMOS ICs take about 75%of the total semiconductor market. Today's
digital ICs may contain several hundreds of millions to more than a
billion transistors on one single 1cm2 chip. They can be subdivided into
three categories: logic, microprocessors and memories. About 10% of
the CMOS ICs are of an analog nature.
Figures 4 to 7 illustrate the evolution in IC technology. Figure 4
shows a discrete BCI07 transistor. The digital filter shown in figure 5
comprises a fewthousand transistors whilethe Digital Audio Broadcast
ing (DAB) chip in figure 6 contains more than six million transistors.
The Intel Pentium4 Xeon dual-core processor in figure 7.25 (section 7.6),
contains 1.3billion transistors. Figure 7showsan 8Gb 63nm multi-level
NAND-flash memory chip.
Figure 8 illustrates the sizes of various semiconductor components,
such as a silicon atom, a single transistor and an integrated circuit, in
perspective. The sizes of an individual MaS transistor are approaching
the details of a virus.
vi
?
2T II lie......· •
156IGT cvpcctcdcapa"-II) ....A:>'..i;;,(ibn
,J:J'/>4(;~II
64G
(:)'4.cg~ii6
16G Gbil
4G .0';
Gbil
IG 0~56Mbil
...... 256~I ••
:...
:~::.. 64M •••0 64Mbil
/:J
~ 16.\1 16Mbil
::: 4~l .04Mbil
:~:: I~I .0" Mbil
~
::. 156k t:1'15bLbil
~ Mk .664kbil
'C'-'' 16k ....0 II>-kbilMO ·DRA t
H
.,.6
Il I·kbilMO ·DRAM
Ii"
156
4·bilITl-coonlcr
64 /fJ dualflip-flop
16
:f!) RTl gale
4
I-f,-=""-,...L--''-=+---=:::;----L,.--...:\.U;:rl'---,-- .,.---,r--r- -.-- .,.---,r--r-
1959 1965 1970 1975 19S0 19S5 19'10 1995 2000 2005 2010 1015 2020 1025
year
Figure 1: Growth in the number ofcomponents per IC
Compound Analog
Di crete :::.1.% MO :::9%
1
:::15.0%
Bipolare 7%
Integrated MO
Circuits :::92%ofthe
Digital
:::85%of integraded :::91%of
theTotal ircuit
MOS
larket Market
Figure 2: Relative semiconductor revenue by IC category (Source: IC
Insights)
Vll
This book provides an insight into allaspectsassociated with CMOS ICs.
The topics presented include relevant fundamental physics. Technology,
design and implementation aspects are also explained and applications
are discussed. CAD tools used for the realisation of ICs are described
while current and expected developments also receive attention.
The contents of this book are based on the CMOS section of an
industry-oriented course entitled 'An introduction to IC techniques'.
Thecourse has been givenalmost threedecades,formerly in Philips,cur
rently in NXP Semiconductors. Continuous revision and expansion of
thecourse material ensures that this book ishighly relevant to the IC in
dustry. The levelofthe discussions makes this book a suitable introduc
tion for designers, technologists, CAD developers, test engineers, failure
analysis engineers, reliability engineers, technical-commercial personnel
and IC applicants. The text is also suitable for both graduates and
undergraduates in related engineering courses.
Considerable effort has been made to enhance the readability of this
book and only essential formulae are included. The large number of di
agrams and photographs should reinforce the explanations. The design
and application examples are mainly digital. This reflects the fact that
more than 90% of all modern CMOS ICs are digital circuits. However,
the material presented willalso provide the analogue designer with a ba
sic understanding ofthe physics, manufacture and operation ofnanome
ter CMOS circuits. Thechapters are summarisedbelow. Foreducational
purposes the first four chapters each start with a discussion on nMOS
physics, nMOS transistor operation, nMOS circuit behaviour, nMOS
manufacturing process, etc. Because the pMOS transistor operation is
fully complementary to that of the nMOS transistor, it is then easier
to understand the operation and fabrication of complementary MOS
(CMOS) circuits. The subjects per chapter are chosen in a very organ
ised and logical sequence so as to gradually built the knowledge, from
Basics to ASICs. The knowledge gathered from each chapter is required
to understand the information presented in the next chapter(s). Each
chapterends with a reference list and exercises. The exercisessummarise
the important topics of the chapter and form an important part of the
complete learning process.
Chapter 1 contains detailed discussions of the basic principles and
fundamental physics of the MOS transistor. The derivation of simple
current-voltage equations for MOS devices and the explanation of their
characteristics illustrates the relationship between process parameters
Vlll
and circuit performance.
The continuous reduction of transistor dimensions leads to increased
deviation between the performance predicted by the simple MOS for
mulae and actual transistor behaviour. The effects of temperature and
the impact of the continuous scaling of the geometry on this behaviour
are explained in chapter 2. In addition to their influence on transistor
and circuit performance,theseeffectscan also reducedevice lifetimeand
reliability.
The various technologiesfor themanufactureofCMOS ICs areexam
ined in chapter 3. After a summary on the available different substrates
(wafers) used as starting material, an explanation ofthe most important
associated photolithographic and processing steps is provided. This pre
cedes a discussion of an advanced nanometer CMOS technology for the
manufacture of modern VLSI circuits.
The design of CMOS circuits is treated in chapter 4. An introduc
tion to the performance aspects of nMOS circuits provides an extremely
useful background for the explanation of the CMOS design and layout
procedures.
MOS technologies and their derivatives are used to realise the spe
cial devices discussed in chapter 5. Charge-coupled devices (CCDs),
CMOS imagers and MOS power transistors are among the special de
vices. Chapter 5concludes thepresentation ofthefundamental concepts
behind BICMOS circuit operation.
Stand-alone memories currently represent about 25% of the total
semiconductor market revenue. However, also in logic and microproces
sor les embedded memoriesrepresent closeto 80%ofthetotal transistor
count. So, of all transistors produced in the world, today, about 90%
end up in either a stand-alone, or in an embedded memory. This share
isexpected to stay at this level or to increase. The majority ofavailable
memory types are therefore examined in chapter 6. The basic struc
tures and the operating principles of the various types are explained.
In addition, the relationships between their respective properties and
application areas is made clear.
Developments in IC technology now facilitate the integration ofcom
plete systems on a chip, which contain several hundreds of millions to
more than a billion of transistors. The various IC design and realisation
techniques used for these VLSI ICs are presented in chapter 7. The ad
vantages and disadvantages of the techniques and the associated CAD
tools are examined. Various modern technologies are used to realise a
IX
separate class ofVLSI ICs, which are specified by applicants rather than
manufacturers. These application-specific ICs (ASICs) are examined in
this chapter as well. Motives for their use are also discussed.
As a result of the continuous increase of power consumption, the
maximum level that can be sustained by cheap plastic packages has
been reached. Therefore, all CMOS designers must have a 'less-power
attitude'. Chapter 8 presents a complete overview of less-power and
less-leakage options for CMOS technologies, as well as for the different
levels of design hierarchy.
Increased VLSI design complexities, combined with higher frequen
ciescreate a higher sensitivity to physical effects. Theseeffects dominate
the reliability and signal integrity of nanometer CMOS ICs. Chapter 9
discusses these effects and the design measures to be taken to maintain
both reliability and signal integrity at a sufficiently high level.
Finally, testing, yield, packaging, debug and failure analysis are im
portant factors that contributeto the ultimatecosts ofan IC.Chapter 10
presents an overview ofthe state-of-the-art techniques that support test
ing, debugging and failure analysis. It also includes a rather detailed
summary on available packaging technologies and gives an insight into
their future trends. Essential factors related to IC production are also
examined; these factors include quality and reliability.
The continuous reduction of transistor dimensions associated with
successive process generations is the subject of the final chapter (chap
ter 11). This scaling has various consequences for transistor behaviour
and IC performance. The resulting increase of physical effects and the
associated effects on reliability and signal integrity are important topics
of attention. The expected consequences of and road blocks for further
miniaturisation are described. This provides an insight into the chal
lenges facing the IC industry in the race towards nanometer devices.
Not all data in this book is completely sprout from my mind. A lot
of books and papers contributed to make the presented material state
of-the-art. Considerable effort has been made to make the reference list
complete and correct. I apologize for possible imperfections.
Acknowledgements
I wish to express my gratitude to all those who contributed to the reali
sation of this book; it is impossible to include all their names. I greatly
value my professional environment: Philips Research labs, of which the
semiconductorresearchdepartment isnowpart ofNXP Semiconductors.
x
It offered me the opportunity to work with many internationally highly
valued colleagues who are all real specialists in their fieldofsemiconduc
tor expertise. Their contributions included fruitful discussions, relevant
texts and manuscript reviews. I would like to make an exception, here,
for my colleagues Marcel Pelgrom and Maarten Vertregt, who greatly
contributed to the discussions held on trends in MOS transistor cur
rents and variability matters throughout this book and Roger Cuppens
and Roelof Salters forthe discussions on non-volatile and random-access
memories, respectively.
I would especially like to thank Andries Scholten and Ronald van
Langevelde for reviewing chapter 2 and for the discussions on leak
age mechanisms in this chapter, Casper Juffermans and Johannes van
Wingerden for their inputs to and Ewoud vreugdenhil (ASM Lithog
raphy) for his review of the lithography section in chapter 3. I would
also like to sincerely thank Robert Lander for his detailed review of
the section on CMOS process technologies and future trends in CMOS
devices and Gerben Doornbos for the correct sizes and doping levels
used in the manufacture ofstate-of-the-art CMOS devices. I appreciate
the many circuit simulations that Octavio Santana has done to create
the tapering-factor table in chapter 4. I am grateful for the review of
chapter 5 on special circuits and devices based on MOS transistor op
eration: Albert Theuwissen (Harvest Imaging) for the section on CCD
and image sensors, Johan Donkers and Erwin Hijzen for the BICMOS
section and Jan Sonsky for the high voltage section. I also appreciate
their willingness to supply me with great photographic material. Toby
Doorn and Ewoud Vreugdenhil are thanked for their review ofthe mem
ory chapter (chapter 6). I appreciate Paul Wielage's work on statistical
simulations with respect to memory yield loss. I thank Ad Peeters for
information on and reviewing the part on asynchronous design in the
low-power chapter (chapter 8). Reliability is an important part ofchap
ter 9, which discusses the robustness of ICs. In this respect I want to
thank Andrea Scarpa for reviewing the hot-carrier and NBTI subjects,
Theo Smedes for the ESD and latch-up subjects and Yuang Li for the
part on electromigration. I also greatly value the work of Bram Kruse
man, Henk Thoonen and Frank Zachariasse for reviewing the sections
on testing, packaging and failure analysis, respectively. I also like to
express them my appreciation forsupplying me with a lot offigures and
photographs, which support and enrich the discussions on these subjects
in chapter 10. Finally, I want to thank Chris Wyland and John Janssen,
xi