Nano Devices and Circuit Techniques for Low-Energy Applications and Energy Harvesting

292 Pages·2016·13.698 MB·English

by  Chong-Min Kyung (eds.)

KAIST Research Series
Chong-Min Kyung Editor
Nano Devices and
Circuit Techniques
for Low-Energy
Applications and
Energy Harvesting
KAIST Research Series
Series editors
Chan Beum Park, Daejeon, Korea, Republic of (South Korea)
Bumki Min, Daejeon, Korea, Republic of (South Korea)
Jae Woo Lee, Daejeon, Korea, Republic of (South Korea)
Jae Seung Jeong, Daejeon, Korea, Republic of (South Korea)
Sang Ouk Kim, Daejeon, Korea, Republic of (South Korea)
Insung S. Choi, Daejeon, Korea, Republic of (South Korea)
More information about this series at http://www.springer.com/series/11753
Chong-Min Kyung
Editor
Nano Devices and Circuit
Techniques for Low-Energy
Applications and Energy
Harvesting
1 3
Editor
Chong-Min Kyung
Department of Electrical Engineering,
Center for Integrated Smart Sensors
KAIST
Daejoen
Korea, Republic of (South Korea)
ISSN 2214-2541 ISSN 2214-255X (electronic)
KAIST Research Series
ISBN 978-94-017-9989-8 ISBN 978-94-017-9990-4 (eBook)
DOI 10.1007/978-94-017-9990-4
Library of Congress Control Number: 2015942486
Springer Dordrecht Heidelberg New York London
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Contents
Part I Devices for Low Energy
Tunneling Field-Effect Transistors for Ultra-Low-Power Application ... 3
Byung-Gook Park
Bulk FinFETs: Design at 14 nm Node and Key Characteristics ........ 33
Jong-Ho Lee
Micro and Nanoelectromechanical Contact Switches
for Logic, Memory, and Power Applications ........................ 65
Yong-Ha Song and Jun-Bo Yoon
Part II Systems and Circuits for Low Energy
Ultralow Power Processor Design with 3D IC Operating
at Sub/Near-Threshold Voltages .................................. 121
Sandeep Samal and Sung Kyu Lim
Energy Harvesting from the Human Body
and Powering up Implant Devices ................................. 147
Ross Kerley, Xiucheng Huang and Dong Sam Ha
Reconfigurable Photovoltaic Array Systems
for Adaptive and Fault-Tolerant Energy Harvesting .................. 181
Naehyuck Chang, Massoud Pedram, Hyung Gyu Lee,
Yanzhi Wang and Younghyun Kim
Low-Power Circuit Techniques for Efficient Energy Harvesting ........ 211
Jaeha Kim, Myeong-Jae Park, Joonseok Yang and Wootaek Lim
v
vi Contents
Part III Materials for Low Energy
Preparation of Porous Graphene-Based Nanomaterials
for Electrochemical Energy Storage Devices ........................ 229
Yuanzhe Piao
Graphene and Two-Dimensional Transition Metal
Dichalcogenide Materials for Energy-Related Applications ............ 253
Gyeong Sook Bang and Sung-Yool Choi
Part I
Devices for Low Energy
Tunneling Field-Effect Transistors
for Ultra-Low-Power Application
Byung-Gook Park
Abstract One of the major roadblocks to further scaling of complementary metal-
oxide semiconductor (CMOS) devices is power consumption. Reduction of power
consumption requires low operation voltage, which requires low threshold voltage.
In order to decrease the threshold voltage without excessive increase of OFF cur-
rent, reduction of the subthreshold swing is essential. To reduce the subthreshold
swing, various carrier injection mechanisms other than thermal carrier injection
have been proposed. Currently, interband tunneling is the most promising mech-
anism and the device that utilizes such a mechanism is a tunneling field-effect
transistor (TFET). After the introduction to the fundamentals of TFETs, various
approaches to increase the drain current of Si TFETs by device structure engineer-
ing are described. The last section focuses on bandgap engineering to enhance the
drain current of TFETs.
Keywords Tunneling field-effect transistor (TFET) · Ultra-low power · Subthreshold
swing · Nanowire · Doping engineering · Tunneling area · Bandgap engineering
1 Introduction
Complementary metal-oxide semiconductor (CMOS) device scaling has been
going on for more than 50 years. The average design rule has shrunk to 70 % of
the previous generation. Such a rate of shrinkage brings roughly an order of mag-
nitude reduction every 20 years. Starting with a few tens of μm design rules in the
1960s, devices with a physical gate length of less than 20 nm are in production
now. In a little more than 50 years, some devices have been shrunk down by more
than three orders of magnitude in size.
B.-G. Park (*)
Seoul National University, Seoul, Korea
e-mail: [email protected]
© Springer Science+Business Media Dordrecht 2016 3
C.-M. Kyung (ed.), Nano Devices and Circuit Techniques for Low-Energy
Applications and Energy Harvesting, KAIST Research Series,
DOI 10.1007/978-94-017-9990-4_1
4 B.-G. Park
In the early 1990s, the first semiconductor technology roadmap (National
Technology Roadmap for Semiconductors, Semiconductor Industry Association,
1992) was developed in the United States of America to guide the semiconductor
industry and set up milestones for technology development. In 1999, the roadmap
was internationalized with a new name, the International Technology Roadmap for
Semiconductors (ITRS). According to the recent ITRS (2013 version) [1], we may
be able to see logic chips made of CMOS devices with a 5 nm feature size in 2028
(Fig. 1).
One of the major roadblocks to further scaling of CMOS devices is power con-
sumption, since the power density of a semiconductor chip increases with scaling
and there is a definite limit of heat dissipation in the conventional cooling system.
The increase in power density originates from the fact that the power consump-
tion of a single device does not scale in proportion to the device area. In the car-
rier velocity saturation limit, the current of a device scales with the channel width,
while the voltage applied to the device is difficult to scale with the channel length.
Thus, the power consumption given by the product of the current and the voltage
does not scale with the area.
Reduction of power consumption requires low operation voltage, which, in
turn, requires low threshold voltage. Reduction of threshold voltage, however, is
accompanied by an exponential increase in the OFF current. In order to decrease
the threshold voltage while maintaining the OFF current low, reduction of the sub-
threshold swing, which is defined as the voltage change required for an order of
magnitude change in current, is essential.
To reduce the subthreshold swing below 60 mV/decade at room temperature,
various carrier injection mechanisms other than thermal carrier injection have been
proposed [2–11]. Interband tunneling can be used for injection of carriers and
Fig. 1 Average design
rule as a function of year.
The predictions of the SIA 104
roadmap and the ITRS are
also plotted )
m
n
(
e
ul 103
R
n
g
si
e
D
ge 102 SIA Roadmap
a
r
e
v SIA Roadmap '97
A
ITRS (DRAM) '13
10
ITRS (Logic) '13
1960 1970 1980 1990 2000 2010 2020 2030
Year