Nano-CMOS and Post-CMOS Electronics

383 Pages·2016·14.5 MB·English

by  Saraju P. Mohanty, Ashok Srivastava

MATERIALS,CIRCUITS&DEVICESSERIES29
Nano-CMOS
and Post-CMOS
Electronics
Othervolumesinthisseries:
Volume2 AnalogueICDesign:TheCurrent-modeApproachC.Toumazou,F.J.Lidgeyand
D.G.Haigh(Editors)
Volume3 Analogue-DigitalASICs:CircuitTechniques,DesignToolsandApplications
R.S.Soin,F.MalobertiandJ.France(Editors)
Volume4 AlgorithmicandKnowledge-basedCADforVLSIG.E.TaylorandG.Russell
(Editors)
Volume5 SwitchedCurrents:AnAnalogueTechniqueforDigitalTechnology
C.Toumazou,J.B.C.HughesandN.C.Battersby(Editors)
Volume6 High-frequencyCircuitEngineeringF.Nibleretal.
Volume8 Low-powerHigh-frequencyMicroelectronics:AUnifiedApproach
G.Machado(Editor)
Volume9 VLSITesting:DigitalandMixedAnalogue/DigitalTechniquesS.L.Hurst
Volume10 DistributedFeedbackSemiconductorLasersJ.E.Carroll,J.E.A.Whiteawayand
R.G.S.Plumb
Volume11 SelectedTopicsinAdvancedSolidStateandFibreOpticSensors
S.M.Vaezi-Nejad(Editor)
Volume12 StrainedSiliconHeterostructures:MaterialsandDevicesC.K.Maiti,
N.B.ChakrabartiandS.K.Ray
Volume13 RFICandMMICDesignandTechnologyI.D.RobertsonandS.Lucyzyn(Editors)
Volume14 DesignofHighFrequencyIntegratedAnalogueFiltersY.Sun(Editor)
Volume15 FoundationsofDigitalSignalProcessing:Theory,AlgorithmsandHardware
DesignP.Gaydecki
Volume16 WirelessCommunicationsCircuitsandSystemsY.Sun(Editor)
Volume17 TheSwitchingFunction:AnalysisofPowerElectronicCircuitsC.Marouchos
Volume18 SystemonChip:NextGenerationElectronicsB.Al-Hashimi(Editor)
Volume19 TestandDiagnosisofAnalogue,Mixed-signalandRFIntegratedCircuits:
TheSystemonChipApproachY.Sun(Editor)
Volume20 LowPowerandLowVoltageCircuitDesignwiththeFGMOSTransistor
E.Rodriguez-Villegas
Volume21 TechnologyComputerAidedDesignforSi,SiGeandGaAsIntegratedCircuits
C.K.MaitiandG.A.Armstrong
Volume22 NanotechnologiesM.Wauteletetal.
Volume23 UnderstandableElectricCircuitsM.Wang
Volume24 FundamentalsofElectromagneticLevitation:EngineeringSustainability
throughEfficiencyA.J.Sangster
Nano-CMOS
and Post-CMOS
Electronics: Devices
and Modelling
Edited by
Saraju P. Mohanty
and Ashok Srivastava
TheInstitutionofEngineeringandTechnology
PublishedbyTheInstitutionofEngineeringandTechnology,London,UnitedKingdom
TheInstitutionofEngineeringandTechnologyisregisteredasaCharityinEngland&
Wales(no.211014)andScotland(no.SC038698).
©TheInstitutionofEngineeringandTechnology2016
Firstpublished2016
ThispublicationiscopyrightundertheBerneConventionandtheUniversalCopyright
Convention.Allrightsreserved.Apartfromanyfairdealingforthepurposesofresearch
orprivatestudy,orcriticismorreview,aspermittedundertheCopyright,Designsand
PatentsAct1988,thispublicationmaybereproduced,storedortransmitted,inany
formorbyanymeans,onlywiththepriorpermissioninwritingofthepublishers,orin
thecaseofreprographicreproductioninaccordancewiththetermsoflicencesissued
bytheCopyrightLicensingAgency.Enquiriesconcerningreproductionoutsidethose
termsshouldbesenttothepublisherattheundermentionedaddress:
TheInstitutionofEngineeringandTechnology
MichaelFaradayHouse
SixHillsWay,Stevenage
Herts,SG12AY,UnitedKingdom
www.theiet.org
Whiletheauthorsandpublisherbelievethattheinformationandguidancegiveninthis
workarecorrect,allpartiesmustrelyupontheirownskillandjudgementwhenmaking
useofthem.Neithertheauthornorpublisherassumesanyliabilitytoanyoneforany
lossordamagecausedbyanyerrororomissioninthework,whethersuchanerroror
omissionistheresultofnegligenceoranyothercause.Anyandallsuchliability
isdisclaimed.
Themoralrightsoftheauthortobeidentifiedasauthorofthisworkhavebeen
assertedbyhiminaccordancewiththeCopyright,DesignsandPatentsAct1988.
BritishLibraryCataloguinginPublicationData
AcataloguerecordforthisproductisavailablefromtheBritishLibrary
ISBN978-1-84919-997-1(hardback)
ISBN978-1-84919-998-8(PDF)
TypesetinIndiabyMPSLimited
PrintedintheUKbyCPIGroup(UK)Ltd,Croydon
Contents
Preface xi
1 High-κ dielectricsanddevicereliability 1
1.1 Introduction 1
1.2 AlloyingHfO andZrO 2
2 2
1.3 AdvancedALDprocess:intermediatetreatment 4
1.4 SPAplasma 5
1.5 CyclicdepositionandSPAplasmatreatmenttoALDHf1−xZrxO2 5
1.5.1 ImpactofZradditionandSPAplasmaonelectrical
properties 8
1.5.2 Reliabilitystudybyconstantvoltagestress 9
1.6 AlincorporationintoHfO 13
2
1.6.1 HfAlO alloystructures 14
x
1.6.2 Al O /HfO bilayerstructures 15
2 3 2
1.6.3 ProblemswithexcessAlincorporation 16
1.6.4 ExtremelylowAlincorporationinHfO 17
2
1.7 Conclusion 27
Acknowledgment 28
References 28
2 Highmobilitynandpchannelsongalliumarsenideandsilicon
substratesusinginterfacialmisfitdislocationarrays 35
2.1 Introduction 35
2.2 IMFversuspseudomorphicgrowth 38
2.3 III-SbonGaAssubstrates 39
2.4 III-Sbonsiliconsubstrates 42
2.4.1 Latticemismatchsolution:IMFlayer 43
2.4.2 Antiphasedomains(APDs) 47
2.4.3 Thermalexpansioncoefficient 50
2.5 GaSbmembranes 51
2.5.1 Substrateremovaltechnique 51
2.5.2 ELOtechnique 53
2.6 InAsandInGaSbchannelsonGaAs 54
2.7 Conclusions 57
References 57
3 Anodicmetal-insulator-metal(MIM)capacitors 61
3.1 Introduction 61
vi Nano-CMOSandpost-CMOSelectronics:devicesandmodelling
3.2 MIMcapacitor 63
3.3 Anodizationfornanoelectronics 64
3.4 AnodicaluminaMIMcapacitors 66
3.4.1 Fabricationprocessflowandcrystallineproperties 67
3.4.2 Capacitanceandvoltagelinearity 67
3.4.3 Leakagecharacteristicsandconductionmechanisms 70
3.5 AnodictitaniaMIMcapacitors 73
3.5.1 Fabricationprocess,oxideformation,andcrystallization 74
3.5.2 Capacitance,voltagelinearity,andleakagecharacteristics 76
3.6 AnodicbilayerMIMcapacitors 79
3.6.1 Fabricationprocessflow 80
3.6.2 Formationofbilayerandcrystallization 81
3.6.3 Capacitance,voltagelinearity,andleakagecharacteristics 82
3.7 Modelingofhigh-k MIMcapacitors 84
3.7.1 Modelingthevoltagelinearity 85
3.7.2 Macroscopicmodel 86
3.7.3 Microscopicmodel 88
3.7.4 Modelverification 89
3.8 Conclusion 90
References 92
4 Graphenetransistors—presentandbeyond 99
4.1 Introduction 99
4.2 Fabricationofgraphene 100
4.3 Propertiesofgraphene 101
4.3.1 Bandstructure 101
4.3.2 Carrierdensity 103
4.3.3 Ambipolarfieldeffect 104
4.3.4 Conductivity 104
4.3.5 Scatteringmechanism 106
4.3.6 High-fieldtransport 108
4.3.7 Low-fieldmobility 109
4.3.8 Substrateandgatedielectrics 110
4.3.9 Jouleheating 112
4.3.10 Contactresistance 112
4.3.11 Quantumcapacitance 113
4.4 Modelingandsimulation 114
4.4.1 Classicaltransport 114
4.4.2 Semiclassicaltransport 115
4.4.3 Quantumtransport 117
4.5 GNRFET 119
4.5.1 Graphenenanoribbon 119
4.5.2 Devicestructure 123
4.5.3 Deviceperformancemetrics 123
4.6 Conclusion 128
References 128
Contents vii
5 Junctionanddoping-freetransistorsforfuturecomputing 139
5.1 Introduction 139
5.2 JLFETlimitations 143
5.3 DopinglessFET 146
5.4 Junctionanddoping-freeFET 148
5.4.1 Junctionanddoping-freeDGFET 149
5.4.2 DopinglessBJT 159
5.5 Conclusion 166
References 166
6 Nanoscalehigh-κ/metal-gateCMOSandFinFETbasedlogic
libraries 169
6.1 Introduction 169
6.2 Summaryofthischapter 172
6.3 HKMGbulkMOSFET 174
6.3.1 HKMGdevicestructure 175
6.3.2 HKMGdevicemodeling 176
6.4 DG-FinFETdevice 178
6.4.1 DG-FinFETdevicestructure 178
6.4.2 DG-FinFETdevicemodeling 180
6.5 Theproposedmethodologyforlogiclibrarycreation 183
6.5.1 Sourcesofvariationandnatureofvariability 183
6.5.2 Statisticallogiclibrarycharacterizationflow 184
6.6 Power,leakage,anddelaymodelsforHKMG
andDG-FinFETtechnology 187
6.6.1 ForHKMG-basedtechnology 187
6.6.2 ForDG-FinFET-basedtechnology 190
6.7 Devicelevelcharacterizationofhigh-κ andFinFET 191
6.7.1 ForHKMGCMOS 191
6.7.2 ForDG-FinFET 199
6.8 PVT-awarelogiclevelcharacterization 204
6.9 Conclusionanddirectionsforfutureresearch 205
Acknowledgment 206
References 206
7 FinFETandreliabilityconsiderationsofnext-generation
processors 213
7.1 Introduction 213
7.2 Background 215
7.2.1 NBTIdegradationmechanism 215
7.2.2 TargetGPUarchitecture 216
7.3 Hybrid-devicewarpscheduler 217
7.3.1 Opportunityforimprovement 217
7.3.2 Two-stagescheduling 219
7.4 Hybrid-devicesequential-accessL2cache 221
7.5 Experimentalsetup 222
viii Nano-CMOSandpost-CMOSelectronics:devicesandmodelling
7.6 Resultanalysis 224
7.6.1 Warpscheduler 224
7.6.2 L2cache 228
7.7 Relatedwork 232
7.7.1 NBTImitigation 232
7.7.2 CharacterizationofFinFETreliability 233
7.7.3 Hybrid-devicedesign 233
7.8 Conclusion 233
References 234
8 Multiple-independent-gate nanowire transistors: from technology
toadvancedSoCdesign 237
8.1 Introduction 237
8.2 Multiple-independent-gatefield-effecttransistors 238
8.2.1 TIGdeviceoverviewandoperation 238
8.2.2 Devicefabricationandelectricalcharacterization 240
8.2.3 Physicalunderstanding 243
8.2.4 Performancepredictions 245
8.3 Circuitdesignopportunities 247
8.3.1 Generalities 247
8.3.2 Compactdatapathdesign 249
8.3.3 Advancedlow-powertechniques 251
8.3.4 Memoryopportunities 254
8.3.5 Case study: implementation of a Polar code decoder with
MIGFETs 257
8.4 Summaryandconclusions 259
Acknowledgment 260
References 260
9 Explorationofcarbonnanotubesforefficientpowerdelivery 265
9.1 Introduction 265
9.2 ModelingofCNTs 266
9.3 CNTsfor2Dpowerdeliverynetwork 269
9.3.1 BranchanalysiswithCNTs 270
9.4 CNTsfor3Dpowerdeliverynetwork 274
9.4.1 CNTTSVanalysis 278
9.4.2 Voltagedropanalysisona3DPDN 280
9.5 Conclusion 284
Acknowledgment 284
References 284
10 Timingdrivenbufferinsertionforcarbonnanotubeinterconnects 287
10.1 Introduction 287
10.2 Problemformulation 290
10.3 CNTinterconnects 290
10.3.1 ResistanceforCNT 291
Contents ix
10.3.2 CapacitanceforCNT 292
10.3.3 Inductiveimpactisnotimportant 293
10.3.4 ElmoredelaymodelforbundledSWCNTsinterconnects 294
10.4 TimingbufferingforCNTinterconnects 294
10.4.1 Addwire 294
10.4.2 Addbuffer 296
10.4.3 Branchmerge 296
10.4.4 Adddriver 297
10.4.5 Pruning 298
10.5 Anexample 299
10.6 Experimentalresults 302
10.6.1 Experimentalsetup 302
10.6.2 Experimentalresults 304
10.7 Conclusions 308
Acknowledgment 309
References 309
11 Memristormodeling–static,statistical,andstochastic
methodologies 313
11.1 Introduction 313
11.2 Staticmodeling 315
11.2.1 TiO thin-filmmemristor 315
2
11.2.2 Memristorstatic(bulk)model 316
11.3 Statisticalmodeling 316
11.3.1 Theoreticalanalysis 316
11.3.2 3Ddevicesamplegenerationflow 319
11.3.3 Theimpactofprocessvariations 322
11.4 Stochasticmodeling 324
11.4.1 ONandOFFstaticstates 324
11.4.2 Dynamicswitchingprocess 324
11.4.3 Stochasticmodelverification 327
11.5 Robustnessofaneuromorphicsystem 329
11.6 Conclusion 332
Acknowledgmentanddisclaimer 332
References 332
12 Neuromorphicdevicesandcircuits 337
12.1 Introduction 337
12.2 Emergingmemorytechnologies 338
12.3 Memristorandresistivememory 340
12.3.1 Memristor 341
12.3.2 Switchingmechanisms 342
12.3.3 Plasticity 345
12.3.4 Memristorintegration 346
12.4 Memristivesynapsecircuits:current-modedesign 347
12.4.1 Overview 347