Table Of ContentMultiprocessor System-on-Chip
Michael Hu¨bner Ju¨rgen Becker
l
Editors
Multiprocessor
System-on-Chip
Hardware Design and Tool Integration
Editors
MichaelHu¨bner Ju¨rgenBecker
KarlsruheInstituteofTechnology(KIT) KarlsruheInstituteofTechnology(KIT)
Institutfu¨rTechnikder Institutfu¨rTechnikder
Informationsverarbeitung Informationsverarbeitung
Vincenz-Prießnitz-Straße1 Vincenz-Prießnitz-Straße1
76131Karlsruhe 76131Karlsruhe
Germany Germany
[email protected] [email protected]
ISBN978-1-4419-6459-5 e-ISBN978-1-4419-6460-1
DOI10.1007/978-1-4419-6460-1
SpringerNewYorkDordrechtHeidelbergLondon
LibraryofCongressControlNumber:xxxxxxx
# SpringerScienceþBusinessMedia,LLC2011
Allrightsreserved.Thisworkmaynotbetranslatedorcopiedinwholeorinpartwithoutthewritten
permissionof the publisher (SpringerScience+Business Media, LLC, 233 SpringStreet, New York,
NY10013,USA),exceptforbriefexcerptsinconnectionwithreviewsorscholarlyanalysis.Usein
connectionwithanyformofinformationstorageandretrieval,electronicadaptation,computersoftware,
orbysimilarordissimilarmethodologynowknownorhereafterdevelopedisforbidden.
Theuseinthispublicationoftradenames,trademarks,servicemarks,andsimilarterms,eveniftheyare
notidentifiedassuch,isnottobetakenasanexpressionofopinionastowhetherornottheyaresubject
toproprietaryrights.
Printedonacid-freepaper
SpringerispartofSpringerScience+BusinessMedia(www.springer.com)
Preface
Forthenextdecade,Moore’sLawisstillgoingtobringhighertransistordensities
allowing Billions of transistors to be integrated on a single chip. However, it
becamemoreandmoreobviousthatexploitingsignificantamountsofinstruction-
levelparallelismwithdeeperpipelinesandmoreaggressivewide-issuesuperscalar
techniques, and using most of the transistor budget for large on-chip caches has
cometoandeadend.Especially,scalingperformancewithhigherclockfrequencies
isgettingmoreandmoredifficultbecauseofheatdissipationproblemsandtoohigh
energyconsumption.Thelatterisnotonlyatechnicalproblemformobilesystems,
butisevengoingtobecomeasevereproblemforcomputingcentersbecausehigh
energy consumption leads to significant cost factors in the budget. Improving
performancecanonlybeachievedbyexploitingparallelismonallsystemlevels.
Therefore, for high-performance computing systems, for high-end servers as
well or for embedded systems, a massive paradigm shift towards multicore archi-
tectures is taking place. Integrating multiple cores on a single chip leads to a
significant performance improvement without increasing the clock frequency.
Multicore architectures offer a better performance/Watt ratio than single core
architectureswithsimilarperformance.
Combining multicore and coprocessor technology promise extreme computing
power for highly CPU-time-consuming applications in scientific computing as
well as for special purpose applications in the embedded area. Especially FPGA-
based accelerators not only offer the opportunity to speedup an application by
implementing their compute-intensive kernels into hardware but also to adapt to
thedynamicalbehaviorofanapplication.
The purpose of this book is to evaluate strategies for future system design
in MPSoC architectures. Both aspects, hardware design and tool-integration
into existing development tools will be discussed. Also the novel trends in
MPSoC combined with reconfigurable architectures are a topic in this book. The
mainemphasisisonarchitectures,design-flow,tool-development,applicationsand
systemdesign.
v
vi Preface
Wekindlywanttothankallauthorsandco-authorsfortheirexcellentcontributions
whichenabledfinallythedevelopmentofthisbook.Furthermorewewanttothankthe
SpringerTeam,namelyMrs.AmandaDavis,Mr.CharlesGlaserandMs.JeyaRuby
fortheirgreatsupportandpatience.
Karlsruhe,Germany Ju¨rgenBecker
MichaelHu¨bner
Contents
1 AnIntroductiontoMulti-CoreSystemonChip–Trends
andChallenges............................................................ 1
LionelTorres,PascalBenoit,GillesSassatelli,MichelRobert,
FabienClermidy,andDiegoPuschini
PartI “ApplicationMappingandCommunicationInfrastructure”
2 ComposabilityandPredictabilityforIndependent
ApplicationDevelopment,Verification,andExecution ................ 25
BennyAkesson,AncaMolnos,AndreasHansson,
JudeAmbroseAngelo,andKeesGoossens
3 HardwareSupportforEfficientResourceUtilization
inManycoreProcessorSystems......................................... 57
A.Herkersdorf,A.Lankes,M.Meitinger,R.Ohlendorf,
S.Wallentowitz,T.Wild,andJ.Zeppenfeld
4 PALLAS:MappingApplicationsontoManycore...................... 89
MichaelAnderson,BryanCatanzaro,JikeChong,EkaterinaGonina,
KurtKeutzer,Chao-YueLai,MarkMurphy,Bor-YiingSu,
andNarayananSundaram
5 TheCaseforMessagePassingonMany-CoreChips.................. 115
RakeshKumar,TimothyG.Mattson,GillesPokam,
andRobVanDerWijngaart
vii
viii Contents
PartII “ReconfigurableHardwareinMultiprocessorSystems”
6 AdaptiveMultiprocessorSystem-on-ChipArchitecture:
NewDegreesofFreedominSystemDesign
andRuntimeSupport..................................................... 127
DianaGo¨hringer,MichaelHu¨bner,andJu¨rgenBecker
PartIII “PhysicalDesignofMultiprocessorSystems”
7 DesignToolsandMethodsforChipPhysicalDesign................. 155
RicardoReis
8 Power‐AwareMulticoreSoCandNoCDesign........................ 167
MiltosD.Grammatikakis,GeorgeKornaros,
andMarcelloCoppola
PartIV TrendsandChallengesforMultiprocessorSystems
9 EmbeddedMulticoreSystems:DesignChallenges
andOpportunities....................................................... 197
DacPham,JimHolt,andSanjayDeshpande
10 High-PerformanceMultiprocessorSystemonChip:
TrendsinChipArchitecturefortheMassMarket................... 223
RobAitken,KrisztianFlautner,andJohnGoodacre
11 InvasiveComputing:AnOverview .................................... 241
Ju¨rgenTeich,Jo¨rgHenkel,AndreasHerkersdorf,
DorisSchmitt-Landsiedel,WolfgangSchro¨der-Preikschat,
andGregorSnelting
Index........................................................................... 269
Part I
“Application Mapping and
Communication Infrastructure”
Chapter 2
Composability and Predictability
for Independent Application Development,
Verification, and Execution
BennyAkesson,AncaMolnos,AndreasHansson,
JudeAmbroseAngelo,andKeesGoossens
Abstract System-on-chip (SOC) design gets increasingly complex, as a growing
number of applications are integrated in modern systems. Some of these applica-
tions have real-time requirements, such as a minimum throughput or a maximum
latency.Toreducecost,systemresourcesaresharedbetweenapplications,making
their timing behavior inter-dependent. Real-time requirements must hence be
verified for all possible combinations of concurrently executing applications,
which is not feasible with commonly used simulation-based techniques. This
chapter addresses this problem using two complexity-reducing concepts: compo-
sability and predictability. Applications in a composable system are completely
isolated and cannot affect each other’s behaviors, enabling them to be indepen-
dently verified. Predictable systems, on the other hand, provide lower bounds on
performance,allowingapplicationstobeverifiedusingformalperformanceanaly-
sis.Fivetechniquestoachievecomposabilityand/orpredictabilityinSOCresources
arepresentedandweexplaintheirimplementationforprocessors,interconnect,and
memoriesinourplatform.
Keywords Composability (cid:1) Predictability (cid:1) Real-Time (cid:1) Arbitration (cid:1) Resource
Management(cid:1)Multi-ProcessorSystem
2.1 Introduction
ThecomplexityofcontemporarySystems-on-Chip(SOC)isincreasing,asagrowing
number of independent applications are integrated and executed on a single chip.
These applications consist of communicating tasks mapped on heterogeneous
multi-processor platforms with distributed memory hierarchies that strike a good
B.Akesson(*)
EindhovenUniversityofTechnology,Postbus513,5600MBEindhoven,TheNetherlands
e-mail:[email protected]
M.Hu¨bnerandJ.Becker(eds.),MultiprocessorSystem-on-Chip:HardwareDesign 25
andToolIntegration,DOI10.1007/978-1-4419-6460-1_2,
#SpringerScience+BusinessMedia,LLC2011
26 B.Akessonetal.
balancebetweenperformance,cost,powerconsumptionandflexibility[14,22,38].
The platforms exploit an increasing amount of application-level parallelism by
enabling concurrent execution of more and more applications. This results in
a large number of use-cases, which are different combinations of concurrently
running applications [15]. Some applications have real-time requirements, such
as a minimum throughput of video frames per second, or a maximum latency for
processingthosevideoframes.Applicationswithreal-timerequirementsarereferred
toasreal-timeapplications,whiletherestarenon-real-timeapplications.Ause-case
cancontainanarbitrarymixofreal-timeandnon-real-timeapplications.
To reduce cost, platform resources, such as processors, hardware accelerators,
interconnect, and memories, are shared between applications. However, resource
sharingcausesinterferencebetweenapplications,makingtheirtemporalbehaviors
inter-dependent. Verification of real-time requirements is often performed by
system-levelsimulation.Thisresultsinthreeproblemswithrespecttoverification,
sinceinter-dependenttimingbehaviorrequiresthatallapplicationsinause-caseare
verifiedtogether.Thefirstproblemisthatthenumberofuse-casesincreasesrapidly
withthenumberofapplications.Ithencebecomesinfeasibletoverifytheexploding
number of use-cases by simulation. This forces industry to reduce coverage and
verifyonlyasubsetofuse-casesthathavethetoughestrequirements[14,37].The
secondproblemisthatverificationofause-casecannotbeginuntilallapplications
it comprises are available. Timely completion of the verification process hence
dependsontheavailabilityofallapplications,whichmaybedevelopedbydifferent
teamsinsidethecompany,orbyindependentsoftwarevendors.Thelastproblemis
that use-case verification becomes a circular process that must be repeated if an
application is added, removed, or modified [23]. Together these three problems
contributetomakingtheintegrationandverificationprocessadominantpartofSOC
development,bothintermsoftimeandmoney[22,23,34].
In this chapter, we address the real-time verification problem using two
complexity-reducing concepts: composability and predictability. Applications in
a composable system are completely isolated and cannot affect each other’s
functional or temporal behaviors. Composable systems address the verification
probleminthefollowingfourways[17]:1)Applicationscanbeverifiedinisolation,
resulting in a linear and non-circular verification process. 2) Simulating only a
single application andits required resources reduces simulationtime compared to
complete system simulations. 3) The verification process can be incremental and
start as soon as the first application is available. 4) Intellectual property (IP)
protection is improved, since the verification process no longer requires the IP of
independentsoftwarevendorstobeshared.Thesebenefitsreducethecomplexityof
simulation-based verification, making it a feasible option with a larger number of
applications. An additional benefit is that composability does not inherently make
anyassumptionsontheapplications,makingitapplicabletoexistingapplications
withoutanymodifications.
Predictablesystems,ontheotherhand,boundtheinterferencefromtheplatform
and between applications. This enables bounds on performance, such as upper
bounds on latency or lower bounds on throughput, to be provided. Applications
