Multiobjective Pathfinding Using Hardware Accelerated Genetic Algorithms

111 Pages·2016·12.92 MB·English

Multiobjective Pathfinding
Using Hardware Accelerated
Genetic Algorithms
Vegard Knutsen Lillevoll
Master’s Thesis Autumn 2016

Multiobjective Pathfinding Using Hardware
Accelerated Genetic Algorithms
VegardKnutsenLillevoll
August1,2016
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Abstract
Multiobjective pathfinding is an extremely computationally expensive
problem, yet it is important for many applications. Classical algorithms
fail as the complexity of the environment increases, and we must look to
othermethodsforfindinghigh-qualitypaths. Thisisespeciallytruewhen
we move beyond assigning a cost to each point on a map, and consider
environmental properties that have a magnitude and a direction, such as
wind.
In this thesis, I present a scalable custom hardware designed by
Geir Åge Noven for evaluating the fitness of paths through real-world
environments. Thehardwareisbasedonagridofprocessingelements,and
each path traverses this grid as its fitness is being calculated. The concept
of topologically folding the environment is discussed. This operation
allows each processing tile to represent multiple areas of the map, which
allowsforevenloaddistributionamongtheprocessingtiles. Theproposed
hardware is compared to other evaluation hardwares, including the GPU,
andsomesimulationsareperformedongeneticalgorithmperformanceon
multiobjectivepathfinding.
I find that the proposed hardware has several properties that makes it
suitable for evaluating path fitness, such as even load distribution among
the processing tiles. I also find that genetic algorithms can continually
improve paths in a real-world terrain for a large number of generations.
Finally, the computational qualities of the proposed hardware and GPU
architecturesarecompared.
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Acknowledgements
I would like to thank my supervisors, Geir Åge Noven, Jim Tørresen and
KyrreGlette,foralltheinspirationandassistanceprovided.
Thanks also go to Morgaine Theresa Wood for proofreading and
editorial advice, and to Tuuli Lehtonen for helping me find many, many
errorsinthisthesis!
The hardware described in this thesis was proposed by Geir Åge
Noven, who also set up the structure of the VHDL evaluator described
in Section 3.4.2. Everything else, including the full CPU evaluator and the
geneticalgorithmapplication,istheworkoftheauthor.
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Contents
Abstract iii
Acknowledgements v
Contents vii
ListofFigures xi
ListofTables xiii
ListofAlgorithms xv
1 Introduction 1
2 Background 5
2.1 GeneticAlgorithms . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.2 Selection . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1.3 Diversity . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Pathfinding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.1 Foundations . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.2 Multi-objectivePathfinding . . . . . . . . . . . . . . . 12
2.3 TypesofHardware . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.1 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.2 GPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.3 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.4 ASIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3 Implementation 19
3.1 GeneticAlgorithm . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.2 GeneticOperations . . . . . . . . . . . . . . . . . . . . 20
3.1.3 DiversityMechanisms . . . . . . . . . . . . . . . . . . 23
3.2 ProposedHardware. . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.2 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.3 Folding . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.4 ProcessingTile . . . . . . . . . . . . . . . . . . . . . . 26
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3.2.5 Packet . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2.6 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.2.7 Hardware . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.3 Parallelism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.4 SimulationUnits . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.4.1 Application . . . . . . . . . . . . . . . . . . . . . . . . 35
3.4.2 Evaluators . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.4.3 Communication . . . . . . . . . . . . . . . . . . . . . . 37
3.4.4 Datasampling. . . . . . . . . . . . . . . . . . . . . . . 37
4 Results 41
4.1 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.1.1 EvaluationOperations . . . . . . . . . . . . . . . . . . 41
4.1.2 ProposedHardwareProperties . . . . . . . . . . . . . 43
4.1.3 GPUPerformanceComparison . . . . . . . . . . . . . 44
4.1.4 GeneticOperations . . . . . . . . . . . . . . . . . . . . 49
4.2 ExperimentSetup . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.3 UniformityofTileUtilization . . . . . . . . . . . . . . . . . . 53
4.3.1 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.3.2 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.4 PreliminaryProposedHardwareExperiments . . . . . . . . 54
4.4.1 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.4.2 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.5 OptimalRateLimit . . . . . . . . . . . . . . . . . . . . . . . . 59
4.5.1 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.5.2 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.6 Increasingnumberofbuffers . . . . . . . . . . . . . . . . . . 62
4.6.1 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.6.2 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.7 EffectofNumberofTilesonTileUtilization . . . . . . . . . . 63
4.7.1 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.7.2 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.8 EffectofNumberofSegmentsonTileUtilization . . . . . . . 64
4.8.1 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.8.2 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.9 ExploringtheGeneticAlgorithmParameterSpace . . . . . . 65
4.9.1 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.9.2 Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5 Conclusions 73
5.1 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.1.1 CostFunction . . . . . . . . . . . . . . . . . . . . . . . 73
5.1.2 TileUtilization . . . . . . . . . . . . . . . . . . . . . . 74
5.1.3 HardwareSuitability . . . . . . . . . . . . . . . . . . . 75
5.1.4 GeneticAlgorithmParameters . . . . . . . . . . . . . 76
5.2 FurtherWork . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5.2.1 GPUImplementation . . . . . . . . . . . . . . . . . . 77
5.2.2 FullRTLImplementation . . . . . . . . . . . . . . . . 77
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