Multi-Threshold CMOS Digital Circuits: Managing Leakage Power

227 Pages·2003·9.337 MB·English

by  Mohab Anis, Mohamed Elmasry (auth.)

Multi-Threshold CMOS Digital Circuits
Managing Leakage Power
Multi-Threshold CMOS Digital Circuits
Managing Leakage Power
MohabAnis
University ofWaterloo
Mohamed Elmasry
University ofWaterloo
SPRINGER SCIENCE+BUSINESS MEDIA, LLC
Library of Congress Cataloging-in-Publication
Title: Multi-Threshold CMOS Digital Circuits Managing Leakage Power
Author (s): Mohab Anis and Mohamed Elmasry
ISBN 978-1-4613-5053-8 ISBN 978-1-4615-0391-0 (eBook)
DOI 10.1007/978-1-4615-0391-0
Copyright © 2003 Springer Science+Business Media New York
Originally published by Kluwer Academic Publishers in 2003
Softcover reprint ofthe hardcover 1st edition 2003
All rights reserved. No part of this publication may be reproduced, stored in a retrieval
system or transmitted in any form or by any means, electronic, mechanical, photo-copying,
microfilming, recording, or otherwise, without the prior written permission of the publisher,
with the exception of any material supplied specifically for the purpose of being entered and
executed on a computer system, for exclusive use by the purchaser of the work.
Permissions forbooks published in the USA: permissions@wkap. com
Permissions for books published in Europe: [email protected]
Printed on acid-free paper.
To
Hussein Anis and Soheir EI-Nahas
and
Elizabeth, Carmen, Samir, Nadia and Hassan Elmasry
Contents
Dedication V
List of Figures Xl
List of Tables xvii
Preface XIX
Acknowledgments xxi
1. INTRODUCTION 1
References 3
2. LEAKAGE POWER: CHALLENGES
AND SOLUTIONS 5
2.1 Introduction 5
2.2 Power Dissipation in CMOS Digital Circuits 6
2.3 Impact of Technology Scaling on Leakage Power 11
2.4 (Vdd-11th) Design Space 15
2.5 Total Power Management 17
2.6 Leakage Power Control Circuit Techniques 17
2.7 Chapter Summary 29
References 31
3. EMBEDDED MTCMOS COMBINATIONAL
CIRCUITS 45
3.1 Introduction 45
3.2 Basic Concept 45
3.3 The Power Minimization Problem 55
Vlll MULTI-THRESHOLD CMOS DIGITAL CIRCUITS
3.4 Algorithms 57
3.5 Choosing the High-11th Value 65
3.6 Chapter Summary 67
References 69
4. MTCMOS COMBINATIONAL CIRCUITS USING
SLEEP TRANSISTORS 73
4.1 Introduction 73
4.2 MTCMOS Design: Overview 73
4.3 Variable Breakpoint Switch Level Simulator [1] 76
4.4 Hierarchical Sizing Based on Mutually Exclusive Discharge
Patterns 79
4.5 Designing High-11th Sleep Transistors, the Average Current
Method [6] 84
4.6 Drawbacks of Techniques 89
4.7 Distributed Sleep Transistors [9] [10] 89
4.8 Clustering Techniques 91
4.9 Hybrid Heuristic Techniques 113
4.10 Virtual Ground Bounce 119
4.11 Results: Taking ground bounce into account 124
4.12 Power Management of Sleep Transistors 127
4.13 Chapter Summary 129
References 131
5. MTCMOS SEQUENTIAL CIRCUITS 135
5.1 Introduction 135
5.2 MTCMOS Latch Circuit 135
5.3 MTCMOS Balloon Circuit 136
5.4 Intermittent Power Supply Scheme 141
5.5 Auto-Backgate-Controlled MTCMOS 141
5.6 Virtual Rails Clamp (VRC) Circuit 143
5.7 Leakage Sneak Paths in MTCMOS Sequential Circuits 144
5.8 Interfacing MTCMOS and CMOS blocks 150
5.9 Impact of the High-11th and Low-11th values on MTCMOS
Sequential Circuit Design 150
Contents ix
5.10 Leakage Feedback Gates 152
5.11 Chapter Summary 156
References 159
6. MTCMOS DYNAMIC CIRCUITS 163
6.1 Introduction 163
6.2 Clock-Delayed Domino Logic: Overview 164
6.3 HS-Domino Logic 168
6.4 MTCMOS CD-Domino Logic: Analysis and Overview 174
6.5 MTCMOS HS-Domino (MHS-Domino) Logic 180
6.6 Domino Dual Cascode Voltage Switch Logic (DDCVSL) 183
6.7 Chapter Summary 188
References 191
7. MTCMOS CURRENT-STEERING CIRCUITS 195
7.1 MOS Current Mode Logic: Overview 195
7.2 Introduction 197
7.3 Minimum Supply Voltage: First Constraint 199
7.4 Saturation Assurance: Second Constraint and the Proposed
MTCMOS Design 201
7.5 A 2.5 Gbitls 1:8 Demultiplexer in MTCMOS MCML 203
7.6 Impact of Using MTCMOS Technology Over MCML
Parameters 206
7.7 Chapter Summary 212
References 213
List of Figures
2.1 Historical Trend of LSls 6
2.2 Sources of load capacitance in a CMOS inverter 7
2.3 Output of an inverter with short-circuit current 8
2.4 Pseudo-NMOS logic gate 9
2.5 Short-channel transistor leakage current mechanisms:
reverse-bias pn junction leakage (ld, weak inversion
(l2), drain-induced barrier lowering (h), gate-induced
drain leakage (l4), punch-through (h), gate oxide tun-
neling (l6), and hot-carrier injection (l7) [6] 10
2.6 Components of Ileakage of a O.35Jlm technology for a
20Jlm wide transistor (currents from various leakage
mechanisms accumulate resulting in a total measured
transistor Ileakage for a given drain bias [11 D. 12
2.7 Projected leakage power over generations [17] 14
2.8 Constant delay curves for Vdd-vth span [12] 16
2.9 Minimum energy point as a function of Vdd and vth [12] 16
2.10 Graphical representation showing reduction of total ac-
tive and standby power D5] 18
2.11 Two NMOS stack in a two-input NAND gate 19
2.12 Variable Threshold CMOS (VTCMOS) 21
2.13 DTCMOS inverter 22
2.14 vth at different channel doping densities [48] 23
2.15 vth at different oxide thicknesses [48] 23
2.16 vth at different channel lengths [48] 24
xii MULTI-THRESHOLD CMOS DIGITAL CIRCUITS
2.17 Multi-Threshold CMOS (MTCMOS) 25
2.18 Multi-Voltage CMOS (MVCMOS) 26
2.19 The Concept of Embedded MTCMOS circuits 28
2.20 Multi-lith gate partitioning showing how critical paths
can change [15] 28
3.1 Path delay distribution of a circuit before and after size
optimization [3] 46
3.2 The Concept of gradated modulation [4] 47
3.3 Gate G and neighboring gates 48
3.4 n-input NAND gate 48
3.5 Equivalent PDN of n-input NAND gate 49
3.6 Leakage current in a 3-input NAND gate [3] 53
3.7 Pseudo-code of High-lith Assignment Algorithm 58
3.8 Mixed-lith schemes [17] 59
3.9 Pseudo-code of Gradated Modulation procedure 62
3.10 Modulated circuit example [4] 63
3.11 High threshold voltage versus leakage current and us-
age ratio of cell [4] 66
3.12 Usage ratios of low-lith cells [4] 67
3.13 Cell-delay distribution of microprocessor components [4] 68
4.1 Sleep transistor modeled as resistor 74
4.2 Worst case discharging scenario 75
4.3 N gates sharing the same virtual ground and discharg-
ing simultaneously 77
4.4 Variable break point switch level simulator function [5] 78
4.5 Inverter chain example showing the three steps for merg-
ing sleep resistors. (Circuit uses Vdd=1.0V, lIth=0.2V,
C=50fF, Imin=0.7J1,m [4]) 80
4.6 Circuits showing how sleep resistors can be combined
in parallel [4] 82
4.7 Logic gates annotated with all possible transition times,
so that sleep resistors can be merged [4] 84
4.8 8-bit parity checker 85
4.9 Simulation for MTCMOS delay [6] 86
4.10 Simulation results presented in [6] 87
4.11 Basic data for the ACM presented in [6] 88
List of Figures Xlll
4.12 4-bit Carry Look-Ahead adder 92
4.13 Timing diagram 94
4.14 2-input NAND example 95
4.15 Random logic network example 96
4.16 Discharge currents in the random logic example 97
4.17 Heuristic for Forming Sub-clusters 99
4.18 Different Isleep values for the 6-bit Multiplier 104
4.19 4-bit CLA adder ftoorplan 105
4.20 Cost function calculation example 106
4.21 Heuristic for Grouping Gates into Clusters 108
4.22 Results:4-bit CLA Adder Floorplan w=(0.5,0.5) 109
4.23 Results:4-bit CLA Adder Floorplan w=(0.9,0.1) 109
4.24 Impact of weights over Pdynamic and Pteakage 110
4.25 A Simple Preprocessing/SP Hybrid Heuristic 114
4.26 An Effective I EQ+ I EQ SP Clustering Hybrid Heuristic 115
4.27 An Effective hQ+IEQ+GATE Preprocessing/SP Clus-
tering Heuristic 116
4.28 Combined Hybrid Heuristics 116
4.29 Computation time for BP, SP and HP 118
4.30 Computation Time for BP,SP and HP (ALU Benchmark) 119
4.31 Transient Response: Ground Bounce 120
4.32 Ground bounce vs. Wsleep 121
4.33 Capacitance associated with virtual ground rail 121
4.34 Reverse conduction 122
4.35 Design Methodology 123
4.36 Comparison: Figure of Merit for benchmarks 126
4.37 Conventional mobile phone running sequence: (a) the
complete sequence and (b) detail of the waiting state. [15] 128
4.38 Power management processor 128
4.39 Power management sequences: (a) without power man-
agement, and (b) with power management [15] 129
5.1 Conventional MTCMOS latch l36
5.2 MTCMOS balloon circuit l37
5.3 Operation of balloon circuit 138
5.4 Typical CMOS MS-FF Circuit l39