MT6735 LTE Smartphone Application Processor Functional Specification

2736 Pages·2015·43.253 MB·English

by  MingTe Lin, CS Chao, Frank Wang

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MT6735 LTE Smartphone Application
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P rocessor Fun ctional Specification
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Version: T 1.5
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Release date: 2015-09-01
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SpecRifications are subject to change without notice.

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© 2015 - 2019 MediaTek Inc.
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This document contains information that is proprietary to MediaTek Inc.
Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited.
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Document Revision History
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Revision Date Author Description S
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1.0 2014-11-20 MingTe Lin Initial draft
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1. Added FHD support for display.
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1.1 2014-12-24 MingTe Lin 2. Updated PMIC wrapper, pericfg controller and

thermal controller chapters.
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1.2 2015-01-20 MingTe Lin Updated Table 2-8, 2-9.
1. Removed ClearMotionTM for DTV-class video
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1.3 2015-02-24 MingTe Lin
2. Removed lane swap support for MIPI_TX.
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3. IRemoved continuous clock support.
1.4 2015-08-03 CS Chao UFpdated Table. 2-21. AUXADC specifications.
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1.5 2015-09-01 Frank Wang Modified SRAMROM description.
NFixed somie typo, removed features optical zoom and
1.6 2015-10-29 MingTe Lin Galileo q
Fixed keypad pull resistance.
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Table of Contents
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Document Revision History .....................................................................S........................ 2
Table of Contents ..................................................................T............................................ 3
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Preface ........................................................................................................................... 12
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1 System Overview .................................................................................................... 13

1.1 Highlighted Features Integrated in MT6735 .......................................................................... 13
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1.2 Platform Features ..................................................................................................................... 15
1.3 MODEM Features .................................................................................................................... 16
1.4 Connectivity Features .....................................D.....................o.................................................... 18
1.5 Multimedia Features ............................................................................................................... 20
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1.6 General Description ................................................................................................................ 22
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2 Product Description ............................................n................................................... 24
2.1 Pin Description ........................................................................................................................ 24
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2.2 Electrical Characteristic .......................................................................................................... 60
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2.3 System Configuration ............................................................................................................. 68
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2.4 Power-on Sequence .....................................a............................................................................ 69
2.5 Analog Baseband ..................................................................................................................... 70
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2.6 Package Information ............................................................................................................... 90
2.7 Ordering Information ......................h........................................................................................ 91
3 MCU and BUS Fabric.... .......................................................................................... 92
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3.1 MCU System ............................................................................................................................ 92
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3.2 On-chip Memory Controller .................................................................................................. 107
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3.3 External Interrupt Controller ................................................................................................ 114
3.4 System Interrupt Controlgler .................................................................................................. 179
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3.5 Infrastructure System Configuration Module ......................................................................201
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3.6 External Memory Interface ................................................................................................... 261
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3.7 DRAM Controller ..o................................................................................................................. 361
3.8 AP_DMA ................................................................................................................................ 462
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3.9 CQDMA ................................................................................................................................... 612
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4 Clock and Powero Control ..................................................................................... 633
4.1 Top Clock Generator ............................................................................................................. 633
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4.2 Top Reset Generate Unit ...................................................................................................... 670
4.3 PMIC Wdrapper ...................................................................................................................... 684
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4.4 Frequency Hopping Controller ............................................................................................. 737
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5 Peripherals ........................................................................................................... 771
5.1 hPericfg Controller ................................................................................................................... 771
5.2 GPIO Control .......................................................................................................................... 812
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5.3 Keypad Scanner ..................................................................................................................... 935
5 .4 UART ..................................................................................................................................... 945
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5.5 USB 2.0 High Speed Dual-Role Controller .......................................................................... 964
5.6 USBPHY Register File ......................................................................................................... 1023
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5.7 SPI Interface Controller ........................................................................L............................... 1047
5.8 MSDC Controller ..................................................................................................................1056
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5.9 AUXADC ............................................................................................................................... 1210
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5.10 I2C/SCCB Controller ........................................................................................................... 1226
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5.11 Pulse-Width Modulation (PWM) ................................................................S....................... 1240
5.12 General-Purpose Timer (GPT) ............................................T................................................ 1278
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5.13 Thermal Controller .............................................................................................................. 1294
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5.14 IRTX ...................................................................................................................................... 1335

5.15 IrDA ...................................................................................................................................... 1344
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5.16 Audio System ........................................................................................................................ 1358
6 Multimedia Subsystem ....................................................................................... 1462
6.1 Multimedia Subsystem ...................................D.....................o................................................ 1462
6.2 SMI_COMMON ................................................................................................................... 1493
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6.3 SMI_LARB ........................................................................................................................... 1516
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6.4 CAM ......................................................F....................n............................................................ 1555
6.5 SENINF_TOP (Sensor Interface)........................................................................................ 1992
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6.6 FDVT ..................................................................................................................................... 2143
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6.7 MDP_RDMA ........................................................................................................................ 2194
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6.8 MDP RSZ .....................................................a........................................................................ 2235
6.9 MDP ROT_DMA (Multimedia Data Path-Rotation DMA) ............................................... 2251
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6.10 Display 2D Sharpness ......................................................................................................... 2281
6.11 DISP_OVL ........................................h.................................................................................... 2315
6.12 DISP RDMA (Display Read Direct Memory Access) .........................................................2375
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6.13 DISP_WDMA ....................................................................................................................... 2391
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6.14 Color Processor .................................................................................................................... 2419
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6.15 DISP CCORR (Display Color Correction Engine) ............................................................. 2460
6.16 DISP AAL (Display Adaptgive Ambient Light Controller) ................................................. 2468
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6.17 DISP GAMMA (Display GAMMA Processing Engine) ..................................................... 2496
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6.18 DISP Dither ......................................................................................................................... 2502
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6.19 DISPLAY PWM Geonerator................................................................................................... 2513
6.20 DPI (Digital Parallel Interface) ........................................................................................... 2518
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6.21 Display Serial Interface ....................................................................................................... 2546
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6.22 MIPI TX Conofiguration Module ......................................................................................... 2593
6.23 JPEG Encoder ...................................................................................................................... 2617
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6.24 JPEG Decoder ..................................................................................................................... 2632
6.25 Video Ddecoder ..................................................................................................................... 2657
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6.26 H.264 Video Encoder .......................................................................................................... 2683
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6.27 MFG ..................................................................................................................................... 2686
6.28 hMultimedia Memory Management Unit (M4U)................................................................ 2702
7 Analog Baseband................................................................................................. 2711
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7.1 AP Mixedsys ......................................................................................................................... 2711

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Lists of Tables

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Table 2-1. Pin coordinate (using LPDDR3) ...........................................................................E.................... 25
Table 2-2. Acronym for pin type ................................................................................................................ 30
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Table 2-3. Detailed pin description (using LPDDR3) ....................................................S.......................... 30
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Table 2-4. Acronym for the table of state of pins ...................................................................................... 39
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Table 2-5. State of pins ............................................................................................................................... 40
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Table 2-6. Acronym for pull-up and pull-down type ............................................................................... 44

Table 2-7. Pin multiplexing, capability and settings ................................................................................ 45
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Table 2-8. Absolute maximum ratings for power supply .........E................................................................ 60
Table 2-9. Recommended operating conditions for power supply .......................................................... 60
Table 2-10. LPDDR3 AC timing parameter table of externDal memory ionterface .................................... 63
Table 2-11. LPDDR2 AC timing parameter table of external memory interface ..................................... 66
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Table 2-12. Mode selection ...........................................I.............................................................................. 68
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Table 2-13. Constant tied pins .................................F.................................................................................. 68
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Table 2-14. Baseband downlink specifications .......................................................................................... 71
Table 2-15. Baseband downlink specifications .N.....................i.................................................................... 73
Table 2-16. LTE_BBTX specifications .................................q.......................................................................74
Table 2-17. C2K_BBTX specifications ........O................................................................................................76
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Table 2-18. ETDAC specifications .............................................................................................................. 77
Table 2-19. APC-DAC specifications ..........................u................................................................................ 78
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Table 2-20. Definitions of AUXADC channels ...........................................................................................79
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Table 2-21. AUXADC specifications .......................................................................................................... 80

Table 2-22. Clock squarer specifKications ........ ............................................................................................ 81
Table 2-23. ARMPLL specifications ............@.............................................................................................. 83
Table 2-24. MAINPLL specifications ........................................................................................................ 84
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Table 2-25. MMPLL specifications ............................................................................................................ 84
Table 2-26. UNIVPLL specifications ..g....................................................................................................... 84
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Table 2-27. MSDCPLL specifications ........................................................................................................ 85
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Table 2-28. WPLL specifications ............................................................................................................... 85
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Table 2-29. WHPLL specificatioons ............................................................................................................ 85
Table 2-30. C2KCPPLL specifications ....................................................................................................... 86
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Table 2-31. C2KDSPPLL specifications ..................................................................................................... 86
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Table 2-32. CR4PLL specoifications ............................................................................................................ 86
Table 2-33. VENCPLL specifications ........................................................................................................ 87
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Table 2-3E4. TVDPLL specifications ........................................................................................................... 87
Table 2-35. LTEDSdPPLL specifications ..................................................................................................... 87
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Table 2-36. APLL1 specifications ............................................................................................................... 88
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Table 2-37. Temperature sensor specifications ........................................................................................ 88
Table 2-38. Thermal operating specifications .......................................................................................... 90
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Table 3-1. Interrupt request list for Cortex-A53 ....................................................................................... 93
Table 3-2z. Memory map of on-chip memory controller .......................................................................... 107
Table 3-3. External interrupt request signal connection ........................................................................ 114

TableR 3-4. Definitions of domains ............................................................................................................ 115
Table 3-5. DRAM bus signal list (refer to DRAMC side) ......................................................................... 361
TOable 3-6. DRAM bus command truth table (LPDDR2/3) .................................................................... 362
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Table 3-7. Relationship between engines and devices ............................................L............................... 462
Table 4-1. PLL related control.................................................................................................................. 636
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Table 4-2. Clock gating settings ............................................................................................................... 636
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Table 5-1. 8*8 single key’s order number in COL/ROW matrix ............................................................ 944
Table 5-2. 3*3 double key’s order number in COL/ROW matrix .............I............................................. 944
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Table 5-3. SPI controller interface ...........................................................T............................................... 1047
Table 5-4. AUXADC: feature list ................................................................................U............................. 1210
Table 5-5. AUXADC: design partition ..............................................N...................................................... 1212
Table 5-6. Operation mode of GPT ..................................................................... .................................... 1278
Table 5-7. Interface of audio sys ................................................E......................m...................................... 1360
Table 6-1. Base addresses of SMI local arbiters ..................................................................................... 1517
Table 6-2. Input format list .................................................D.....................o...............................................2194
Table 6-3. Functional specifications of resizers .................................................................................... 2235
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Table 6-4. Hardware specifications of resizers ..................................................................................... 2236
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Table 6-5. ROT_DMA OFST_ADDR settings for rotation/flip ............................................................ 2276
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Table 6-6. VIDO UV SEL for YUV420 format cooperated with CRSP ................................................ 2276
Table 6-7. Data map ...........................................N.................................................................................... 2544
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Table 6-8. Sequence to enable module clock ........................................................................................ 2578
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Table 6-9. Sequence to enable high-speed clock .................................................................................. 2578
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Table 6-10. Sequence of exiting ultra-low power modea on clock lane ................................................. 2578
Table 6-11. Sequence of sleep-in control (entering ultra-low power mode) ....................................... 2578
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Table 6-12. Sequence of sleep-out control (exiting ultra-low power mode) ....................................... 2579
Table 6-13. DPHY timing parameters register sehttings ........................................................................ 2579

Table 6-14. DPHY global operation timing parameter defined by MIPI spec .................................... 2580
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Table 6-15. Config. field description of main instruction ..................................................................... 2582
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Table 6-16. Type-0 Tx example .............................................................................................................. 2583
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Table 6-17. Type-1 Tx example ............................................................................................................... 2584
Table 6-18. Type-2 Tx example ...........g................................................................................................... 2585
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Table 6-19. Type-3 Tx example .............................................................................................................. 2586
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Table 6-20. Command mode status in debugging register .................................................................. 2586
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Table 6-21. Example of TE signaling detection ..................................................................................... 2590
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Table 6-22. Example of external TE pin detection ................................................................................ 2591
Table 6-23. ExaImple of shorht packet transmission in video mode ....................................................... 2591
Table 6-24. EDxample of long packet transmission in video mode ....................................................... 2592
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Table 6-25. MIPI PLL initial sequence ................................................................................................... 2613
Table 6-2E6. MIPI PLLa de-initial sequence .............................................................................................2614
Table 6-27. Software control mode example .......................................................................................... 2615
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TablMe 6-28. MIPI PLL initial sequence with SSC enable ....................................................................... 2615
Table 6-29. VDEuC base address ............................................................................................................. 2659
Table 6-30. Power down control and clock selection ........................................................................... 2663
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Table 6-31. Checksum register ............................................................................................................... 2666
Table 6-32. Main features ...................................................................................................................... 2683
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List of Figures

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Figure 1-1. High-level MT6735 functional block diagram ....................................................E..................... 14
Figure 1-2. Block diagram of MT6735 ....................................................................................................... 23
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Figure 2-1. Ball map view for LPDDR3 ...........................................................................S.......................... 24
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Figure 2-2. Ball map view for LPDDR2 ..................................................................................................... 25
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Figure 2-3. IO types in state of pins .......................................................................................................... 44
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Figure 2-4. Basic timing parameter for LPDDR3 commands .................................................................. 62

Figure 2-5. Basic timing parameter for LPDDR3 write ............................................................................ 62
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Figure 2-6. Basic LPDDR3 read timing parameter .................................................................................. 63
Figure 2-7. Basic timing parameter for LPDDR2 commands .................................................................. 65
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Figure 2-8. Basic timing parameter for LPDDR2 write ........................................................................... 66
Figure 2-9. Basic timing parameter for LPDDR2 read ......................c....................................................... 66
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Figure 2-10. Power on/off Sequence by pressing PWRKEY .................................................................... 69
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Figure 2-11. Block diagram of LTE_BBRX-ADC ........................n............................................................... 71
Figure 2-12. Block diagram of C2K_BBRX-ADC ....................................................................................... 73
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Figure 2-13. Block diagram of LTE_BBTX ................................................................................................74
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Figure 2-14. Block diagram of C2K_BBTX ................................................................................................76
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Figure 2-15. Block diagram of ETDAC ...........................a............................................................................ 77
Figure 2-16. Block diagram of APC-DAC (same architecture for two APC-DACs) ................................. 78
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Figure 2-17. Block diagram of AUXADC ....................................................................................................79
Figure 2-18. Block diagram of ARMPLL .............h...................................................................................... 82

Figure 2-19. Block diagram of PLLGP ....................................................................................................... 83
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Figure 2-20. Outlines and dimensions of VFBGA 12.6mm*12.6mm, 641 balls, 0.4mm pitch package 90
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Figure 2-21. Top mark of MT6735 .............................................................................................................. 91
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Figure 3-1. Block diagram of on-chip memory controller ....................................................................... 107
Figure 3-2. Security memory protectiogn scheme .................................................................................... 108
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Figure 3-3. Block diagram of external interrupt controller .................................................................... 114
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Figure 3-4. System level block diagram of system interrupt controller ................................................. 179
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Figure 3-5. Block diagram of syostem interrupt controller ...................................................................... 180
Figure 3-6. DCM in action ........................................................................................................................ 201
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Figure 3-7. Top AXI fabric and control blocks ........................................................................................ 202
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Figure 3-8. EMI/DRAM coontroller top connection ................................................................................ 262
Figure 3-9. Block diagram of DRAM controller ...................................................................................... 364
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Figure 3-10. APDMA block diagram ........................................................................................................ 463
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Figure 3-11. APDMA block diagram ......................................................................................................... 612
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Figure 4-1. Block diagram of clock architecture ..................................................................................... 633
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Figure 4-2. Example of clock multiplixer ................................................................................................ 634
Figure 4-3. PhLL block diagram ................................................................................................................ 635
Figure 4-4. ABIST FMETER structure .................................................................................................... 637 MediaTek Confidential A
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Figure 4-5. CKGEN FMETER structure .................................................................................................. 637

Figure 4-6. Block diagram of top reset generation unit ......................................................................... 670
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Figure 4-7. PMIC_WRAP architecture .................................................................................................... 684
Figure 4-8. Block diagram of frequency hopping controller .................................................................. 738
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Figure 5-1. Block diagram of pericfg controller .......................................................L................................ 771
Figure 5-2. GPIO block diagram ............................................................................................................... 812
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Figure 5-3. 8x8 keypad matrix (64 keys) ................................................................................................ 936
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Figure 5-4. 3x3 keypad matrix (18 keys) ................................................................................................. 936
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Figure 5-5. 8x8 keypad scan waveform ...........................................................................S........................ 937
Figure 5-6. 5*5 keypad scan waveform ...................................................T................................................ 937
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Figure 5-7. One key pressed with de-bounce mechanism denoted ....................................................... 938
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Figure 5-8. (a) Two keys pressed, case 1; (b) Two keys pressed, case 2 ................................................ 938

Figure 5-9. Block diagram of UART ........................................................................................................ 946
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Figure 5-10. USB controller block diagram ............................................................................................. 965
Figure 5-11. USBPHY RegFile block diagram ....................................................................................... 1023
Figure 5-12. Pin connection between SPI master and SPI Dslave ............o............................................... 1047
Figure 5-13. SPI transmission formats ................................................................................................... 1047
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Figure 5-14. Operation flow with or without PAUSE mode ................................................................. 1049
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Figure 5-15. CS_N de-assert mode ..........................F....................n.......................................................... 1049
Figure-5-16. Block diagram of SPI ......................................................................................................... 1049
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Figure 5-17. Block diagram of MSDC controller .................................................................................... 1057
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Figure 5-18. Block diagram of AUXADC ................................................................................................. 1211
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Figure 5-19. SAR ADC architecture and conversion ......a........................................................................ 1212
Figure 5-20. Block diagram of I2C ......................................................................................................... 1229
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Figure 5-21. Generation procedure of PWM ......................................................................................... 1240
Figure 5-22. Block diagram of APXGPT ..............h................................................................................... 1279
Figure 5-23. Implementation of C MOS temperature sensor ................................................................ 1295
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Figure 5-24. Block diagram of system temperature measurement ......................................................1296
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Figure 5-25. Block diagram of system temperature measurement ...................................................... 1297
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Figure 5-26. Programming flow ............................................................................................................. 1330
Figure 5-27. Immediate measurementg programming flow ................................................................... 1332
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Figure 5-28. Interrupt condition of high/low temperature monitoring .............................................. 1333
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Figure 5-29. Finite state machine of high/low temperature monitoring ............................................. 1333
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Figure 5-30. Interrupt conditiono of high/low offset monitoring .......................................................... 1333
Figure 5-31. Finite state machine of high/low offset monitoring ......................................................... 1334
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Figure 5-32. Logic representation for NEC protocol ............................................................................. 1335
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Figure 5-33. Pulse train ion transmission of NEC protocol .................................................................... 1335
Figure 5-34. A message is started by a 9ms AGC burst ......................................................................... 1336
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Figure 5-35. A repeat code is transmitted every 110ms ......................................................................... 1336
Figure 5-36. Codingd method for RC5 protocol....................................................................................... 1337
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Figure 5-37. Lead pulse in RC6 protocol ................................................................................................ 1337
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Figure 5-38. Coding method for RC6 protocol ......................................................................................1338
Figure 5-39. hTrailer pulse in RC6 protocol ............................................................................................1338
Figure 5-40. Block diagram of IrDA ....................................................................................................... 1344
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Figure 5-41. Block diagram of audio sys ................................................................................................. 1359
Figure 6-1. MDP function blocks of multimedia partition .................................................................... 1463
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Figure 6-2. DISP function blocks of multimedia partition ................................................................... 1463
Figure 6-3. SMI_COMMON and neighbor blocks ................................................................................. 1493
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Figure 6-4. SMI local arbiter block diagram ............................................................L.............................. 1516
Figure 6-5. Definition of RIP and ROP .................................................................................................. 2143
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Figure 6-6. Example of face detection with 24x24 Macro-window ......................................................2144
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Figure 6-7. FDE operation flow ..............................................................................................................2144
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Figure 6-8. Register setting timing diagram ...................................................................S....................... 2145
Figure 6-9. Hardware FDVT processing flow in one frame ...................T............................................... 2145
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Figure 6-10. Support clipping from source frame buffer ......................................................................2194
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Figure 6-11. Block diagram of DISP MDP_RDMA ................................................................................ 2195

Figure 6-12. SW control flow ................................................................................................................. 2234
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Figure 6-13. HW FSM and mutex control flow ..................................................................................... 2234
Figure 6-14. Separate 1D FIR operaiton ................................................................................................ 2236
Figure 6-15. 4 tap cubic block diagram (Luma and ChromDa data, in MTo6735 4tap changes to 6tap)
................................................................................................................................................................. 2237
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Figure 6-16. Cubic accumulation (scaling ratio = 1x) ........................................................................... 2238
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Figure 6-17. Cubic accumulation (scaling ratio = 1/F2x) .............n.......................................................... 2238
Figure 6-18. Suggested algorithm v.s. supported size .......................................................................... 2239
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Figure 6-19. Programming guide ............................................................................................................ 2241
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Figure 6-20. Block diagram of ROT_DMA ............................................................................................ 2251
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Figure 6-21. Firmware settings of OFST_ADDR in 0° raotation (scan-line)........................................ 2275
Figure 6-22. Firmware settings of OFST_ADDR in 90° rotation (scan-line) ..................................... 2275
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Figure 6-23. Firmware settings of OFST_ADDR in 180° rotation (scan-line) ................................... 2276
Figure 6-24. Firmware settings of OFST_ADDRh in 270° rotation (scan-line) ................................... 2276
Figure 6-25. Probability of crossin g 256-byte boundary by random access ....................................... 2279
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Figure 6-26. Scan-line request without considering 256-byte boundary ............................................ 2279
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Figure 6-27. Scan-line request considering 256-byte boundary .......................................................... 2280
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Figure 6-28. 4-16 burst in 270° rotation with/without flip ................................................................. 2280
Figure 6-29. Block diagram of displayg 2D sharpness ........................................................................... 2281
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Figure 6-30. Block diagram of sharpness core ..................................................................................... 2281
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Figure 6-31. Visual effect of 2-dimensional sharpness ......................................................................... 2282
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Figure 6-32. Visual effect of peaoking by color ....................................................................................... 2282
Figure 6-33. Usage scenarios .................................................................................................................. 2313
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Figure 6-34. Gain curve control of sharpness ........................................................................................ 2313
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Figure 6-35. Luma mappoing curve example .......................................................................................... 2314
Figure 6-36. Block diagram of DISP_OVL ............................................................................................. 2316
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Figure 6-37. Typical DISP_OVL programming procedure .................................................................. 2374
Figure 6-38. Block ddiagram of RDMA engine ....................................................................................... 2375
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Figure 6-39. General programming sequence ...................................................................................... 2389
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Figure 6-40. Basic memory mode configuration .................................................................................. 2390
Figure 6-41. hProgrammable color matrix .............................................................................................. 2390
Figure 6-42. Byte/RGB swap ................................................................................................................. 2390
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Figure 6-43. Block diagram of DISP_WDMA ........................................................................................ 2391
Figure 6-44. Typical DISP_WDMA programming sequence .............................................................. 2418
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Figure 6-45. Block diagram of color processor ..................................................................................... 2420
Figure 6-46. 20 hue phases distribution ............................................................................................... 2456
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Figure 6-47. Partial hue adjustment example ..........................................................L............................. 2457
Figure 6-48. Contrast/brightness adjustment example ....................................................................... 2457
A
Figure 6-49. Chroma boost demonstration........................................................................................... 2458
E
Figure 6-50. Example of partial S adjustment for one hue phase ....................................................... 2458
I
Figure 6-51. Illustration of global saturation adjustment ..............................................S...................... 2459
Figure 6-52. Block diagram of color correction ......................................T.............................................. 2460
U
Figure 6-53. Visual effect of color correction ........................................................................................ 2460
N
Figure 6-54. Block diagram of AAL processor ...................................................................................... 2468

Figure 6-55.Visual effect of DRE enhancement .................................................................................... 2469
m
E
Figure 6-56. Visual effect of gamma correction .................................................................................... 2496
Figure 6-57. Illustration of general timing relationship ....................................................................... 2543
Figure 6-58. Data/Clock timing ..........................................D.....................o.............................................. 2544
Figure 6-59. Programming flow diagram .............................................................................................. 2545
c
I
Figure 6-60.Registers for data lane timing parameters ........................................................................ 2581
.
Figure 6-61. Registers for clock lane timing parameFters ............n........................................................... 2581
Figure 6-62. Register for BTA timing parameters ................................................................................. 2581
N
i
Figure 6-63. DSI command queue instruction format ......................................................................... 2582
q
Figure 6-64. Type-0 instruction format ................................................................................................ 2583
O
Figure 6-65. Type-1 instruction format ..........................a....................................................................... 2584
Figure 6-66. Type-2 instruction format ................................................................................................ 2585
u
C
Figure 6-67. Type-3 instruction format ................................................................................................. 2585
Figure 6-68. Non-burst transmission: sync-pulshe mode ..................................................................... 2587
Figure 6-69. Sync-pulse mode lin e period ............................................................................................ 2587
K
Figure 6-70. Sync-pulse mode word-count parameters ....................................................................... 2588
@
Figure 6-71. Non-burst transmission: Sync-event mode...................................................................... 2588
E
Figure 6-72. Sync-event mode line period ............................................................................................ 2589
Figure 6-73. Sync-event mode word-cgount parameters ....................................................................... 2589
T
Figure 6-74. Burst mode transmission .................................................................................................. 2590
n
Figure 6-75. Initial waveform of MIPI PLL ............................................................................................ 2613
A
Figure 6-76. Procedure of JPEGo encoder ............................................................................................... 2617
Figure 6-77. Memory footprint of source frame buffer .........................................................................2619
I h
Figure 6-78. Basic structure of JPEG files ............................................................................................ 2632
D
Figure 6-79. Supported saompling format of input JPEG file ............................................................... 2633
Figure 6-80. Memory footprint of source frame buffer ....................................................................... 2635
a
E
Figure 6-81. Block diagram of video decoder........................................................................................ 2658
Figure 6-82. Interfadce of VDEC ............................................................................................................. 2658
M
Figure 6-83. VDEC hardware architecture ........................................................................................... 2659
u
Figure 6-84. VLD hardware architecture .............................................................................................. 2660
Figure 6-85.h VDEC decoding flow ......................................................................................................... 2660
Figure 6-86. Software reset and power control .....................................................................................2661
z
Figure 6-87. Software reset and power control (turn off VDEC auto power down) ........................... 2662
Figure 6-88. Initial fetch and initial Barrel-shift .................................................................................. 2664
R
Figure 6-89. Flow chart of initial fetch and initial Barrel-shift ........................................................... 2664
Figure 6-90. Block diagram of bitstream buffer and barrel shifter ..................................................... 2665
O
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