Table Of ContentMT6186M RF System Datasheet
Version: 0.2
Release date: 2019-01-18
Specifications are subject to change without notice.
© 2019 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc.
. Unauthorized reproduction or disclosure of this information in whole or in part is strictly prohibited
MT6186M
RF System Datasheet
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Document Revision History
Revision Date Author Description
0.1 2019-01-11 Ee Sze Khoo Initial draft
1. Updated Chapter 5, TX specifications.
0.2 2019-01-18 Johoo Lin
2. Updated supported band table in 1.2.
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Table of Contents
Document Revision History .............................................................................................................................. 2
Table of Contents............................................................................................................................................. 3
1 Introduction .......................................................................................................................................... 5
1.1 Overview ........................................................................................................................................... 5
1.2 Key Features ...................................................................................................................................... 5
2 Block Diagram and Application Diagram ................................................................................................ 7
3 General Specifications ........................................................................................................................... 9
3.1 Packaging .......................................................................................................................................... 9
3.2 IC Marking ....................................................................................................................................... 10
3.3 RF I/O List ........................................................................................................................................ 11
3.4 Ball Assignment ............................................................................................................................... 13
3.5 Absolute Maximum Ratings ............................................................................................................ 14
3.6 Operating Conditions ...................................................................................................................... 15
3.7 BSI Speed ......................................................................................................................................... 16
4 Supply Specification ............................................................................................................................ 17
4.1 External Power Supplies and Interfaces .......................................................................................... 17
5 Transmitter ......................................................................................................................................... 18
5.1 TX Block Diagram............................................................................................................................. 18
5.2 4G FDD/TDD Transmitter Chain Performance Specification ........................................................... 21
5.3 4G FDD/TDD CCA Transmitter Chain Performance Specification.................................................... 24
5.4 3G FDD Transmitter Chain Performance Specification ................................................................... 25
5.5 3G TDD Transmitter Chain Performance Specification ................................................................... 26
5.6 3G C2K Transmitter Chain Performance Specification .................................................................... 27
5.7 2G Transmitter Chain Performance Specification ........................................................................... 28
5.8 Transmitter Power Control Specification ........................................................................................ 29
6 Receiver............................................................................................................................................... 30
6.1 TD-SCDMA Specification ................................................................................................................. 32
6.1.1 TD-SCDMA RX Specification .......................................................................................... 32
6.1.2 TD-SCDMA RX Specification (For eLNA Application) ..................................................... 32
6.2 GGE (2G GSM/GPRS/EDGE) Specification ....................................................................................... 33
6.2.1 GGE RX Specification ..................................................................................................... 33
6.2.2 GGE RX Specification (For eLNA Application) ................................................................ 33
6.3 CDMA Specification ......................................................................................................................... 34
6.3.1 CDMA RX Specification .................................................................................................. 34
6.3.2 CDMA RX Specification (For eLNA Application) ............................................................. 34
6.4 WCDMA Specification ..................................................................................................................... 36
6.4.1 WCDMA RX Specification .............................................................................................. 36
6.4.2 WCDMA RX Specification (For eLNA Application) ......................................................... 37
6.5 LTE Specification ............................................................................................................................. 39
6.5.1 LTE RX Specification....................................................................................................... 39
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6.5.2 LTE RX Specification (For eLNA Application) ................................................................. 41
7 Digital Control Interfaces ..................................................................................................................... 45
7.1 Introduction .................................................................................................................................... 45
7.2 Power-on Reset ............................................................................................................................... 46
7.3 BSI Interface .................................................................................................................................... 47
8 Reference Clock Specification .............................................................................................................. 48
8.1 Reference Input Buffer Specification (CLK26M) .............................................................................. 48
8.2 26MHz Clock Specification .............................................................................................................. 48
Lists of Figures
Figure 2-1. RFSYS block diagram ............................................................................................................................. 7
Figure 3-1. Ball map .............................................................................................................................................. 13
Figure 5-1. TX block diagram (TX0) ....................................................................................................................... 19
Figure 6-1. RX block diagram ................................................................................................................................ 30
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MT6186M
RF System Datasheet
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1 Introduction
1.1 Overview
MT6186M is a multi-mode multi-band highly integrated transceiver in 28nm CMOS. This document describes
the performance targets for the RF stand-alone chip to be embedded in the overall platform.
1.2 Key Features
Full multi-mode RF solution (C2K/GGE/WCDMA/TDSCDMA/LTE/LTE-CA)
o Multi-band LTE/WCDMA/TD-SCDMA/GGE/C2K
64QAM UL/256QAM DL (HSPA+/LTE) o
o C2K/2G/3G/4G co-banding
o Supports RxD (15 RxD ports)
o Supports SRLTE
Direct conversion transmitter (LTE/3G/8-PSK) and DFM for GMSK
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o Dedicated power detection circuits for power control over specific power range
o 2LB+2MB+1HB/UHB TX0 output port
Hybrid Direct-Conversion (4G/3G/C2K)/Low-IF (GGE, DC-HSDPA) receiver
o 15+15 Rx input ports
o 2+2 sets single ended RXIF IQ outputs.
Supports external LNA at RxP and RxD
Low supply current and operation directly from dual DC-DC converters
Supports RF Calibration features for key RX and TX specifications (image rejection, LO feed-through, IIP2,
DC offset, RC corner)
Temperature measurement sub-system
LTE carrier aggregation (CA)
o Supports 1UL+2DL CA.
Supports RX 4*4 MIMO for MHB case
Supports LTE Power Class 2 high-power UE (HPUE) in band 41 up to 40MHz
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2 Block Diagram and Application Diagram
LAA/UHB(x2) MHB(x8) LB(x5) HB/UHB MB (x2) LB (x2) DET input
XRPXRD FroI-mI TTG detroppus MSG iXT0 (w)
PDXXR0/R0 XRS0 XT0 revirD MB revirD LB
U/HB
revirD
DPXXR1/R1 XRS1
AIT AIT
DET PATH LO
2 2 From SRX0
AGP AGP
Controller
DCO
STX-dig
STX0
2 2 4 2
Figure 2-1. RFSYS block diagram
RXIF IQ output loading model
MT6186M D die
R =150ohm R =1ohm
lay EVB
OUT
R
Clay+pkg=2pF CEVB,Max=15pF Clay+pkg=2pF adc
For the applications with bandwidth beyond LTE 30MHz, for example NC-CA, we highly recommend that the
ding should be small enough (<15pF) to avoid extra drooping in band-edge and pPeCrBfo lromaance
degradation. Inevitably, in some special cases, the PCB IQ traces may be longer and make PCB loading larger,
and the value will be up to several tens of pF. In these cases, limited performance can only be achieved. For
example, the maximal throughput will be degraded.
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PCB trace requirements of RX IF interface:
1. Capacitance loading < 15pF
2. Mismatch between capacitance of I path and Q path < 10%
3. The trace to trace isolation has been defined in system application note. Pay attention to the isolation
between traces for required performance.
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3 General Specifications
3.1 Packaging
FCCSP is currently considered for this product.
Parameter Single die
Body size (width/length/height) 4.8*5.3*0.82mm
Ball spacing 0.35mm
Ball array 17*19
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3.2 IC Marking
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