Modeling & Analysis of a Closed Loop Class D Audio Amplifier For PSR Improvement By Bijeta ...

101 Pages·2012·5.04 MB·English

Modeling & Analysis of a Closed Loop Class D Audio Amplifier

For PSR Improvement

By

Bijeta Chakraborty

A Thesis Presented in Partial Fulfillment
of the Requirements for the Degree
Master of Science

Approved October 2012 by the
Graduate Supervisory Committee:

Bertan Bakkaloglu, Chair
Douglas Garrity
Sule Ozev

ARIZONA STATE UNIVERSITY

December, 2012
ABSTRACT
Class D Amplifiers are widely used in portable systems such as mobile
phones to achieve high efficiency. The demands of portable electronics for low
power consumption to extend battery life and reduce heat dissipation mandate
efficient, high-performance audio amplifiers. The high efficiency of Class D
amplifiers (CDAs) makes them particularly attractive for portable applications.
The Digital class D amplifier is an interesting solution to increase the efficiency of
embedded systems. However, this solution is not good enough in terms of PWM
stage linearity and power supply rejection. An efficient control is needed to
correct the error sources in order to get a high fidelity sound quality in the whole
audio range of frequencies. A fundamental analysis on various error sources due
to non idealities in the power stage have been discussed here with key focus on
Power supply perturbations driving the Power stage of a Class D Audio Amplifier.
Two types of closed loop Digital Class D architecture for PSRR improvement
have been proposed and modeled. Double sided uniform sampling modulation
has been used. One of the architecture uses feedback around the power stage
and the second architecture uses feedback into digital domain. Simulation &
experimental results confirm that the closed loop PSRR & PS-IMD improve by
around 30-40 dB and 25 dB respectively.

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ACKNOWLEDGMENTS
It has been an honour to be able to complete my Master of Science Degree from
Arizona State University. First of all I would like to express my deep and sincere
gratitude to Prof.Bertan Bakkaloglu. This research project would not have been
possible without the support and constant guidance of Prof.Bertan Bakkaloglu.
He has been abundantly helpful and offered timely support and guidance to me
throughout. He has always shown confidence and trust in me which have kept
me motivated.

I would also like to wholeheartedly thank Prof. Sule Ozev and Prof. Douglas
Garrity for being a part of my committee member in spite of their busy schedule.

I wish to express love and gratitude to my beloved family members and few close
friends; for their understanding & endless love & helping me throughout all the
odd times of my life so far.
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TABLE OF CONTENTS
Page
LIST OF TABLES ..................................................................................................... v
LIST OF FIGURES .................................................................................................. vi
CHAPTER
1 INTRODUCTION ................................................................................. 1
1.1 What is Sound ? ........................................................................ 1
1.2 Basics of CLASS D Audio Amplification ................................... 5
1.2.1 Analog vs. Digital Class D .............................................. 10
1.3 Motivation For Closed Loop Digital Class D ........................... 13
1.4 Report Organization ............................................................... 13
2 DIGITAL CLASS D AMPLIFICATION ................................................ 14
2.1 Interpolation & Noise Shaping ................................................. 15
2.2 Digital Pulse Modulation Techniques ...................................... 18
2.3 Power Stage ........................................................................... 21
2.4 Demodulation Filter ............................................................... 23
3 SOURCES OF ERROR IN CLASS D POWER STAGE ..................... 25
3.1 Brief overview of Switching Device .......................................... 26
3.2 Analysis of Pulse Amplitude Errors ......................................... 29
3.3 Mathematical Derivation for PSRR & PS-IMD ......................... 29
4 EXISTING FEEDBACK STRATEGIES FOR DIGITAL CLASS D ...... 34
4.1 Non Linear Feedback & Predistortion ...................................... 34
4.2 Digital Class D with Analog Loop Feedback ............................ 38
4.3 Digital Class D with Error Remodulation ................................. 40
5 DIGITAL CLASS D: MODELLING & SYSTEM DESIGN .................... 44
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CHAPTER Page
5.1 Modulator Design .................................................................... 44
5.2 Sampling Technique : UPWM ................................................. 49
5.3 Power Stage & Demodulation Filter ........................................ 55
5.4 Feedback Strategies .............................................................. 60
5.4.1 Feedback into the Digital Domain .................................... 62
5.4.2 Duty Ratio Correction based feedback .......................... 66

6 CONCLUSION & FUTURE SCOPE ................................................... 71
REFERENCES ......................................................................................... 74
APPENDIX
A SIMULINK MODELS ........................................................................ 76
B MATLAB CODES AND ALGORITHM .............................................. 83

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LIST OF TABLES
Table Page
1. Harmonic components UADD vs. UADS ......................................................... 20
2. PSR and PS-IMD (open loop vs. close loop) CLASS D ................................... 72

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LIST OF FIGURES
Figure Page
1. Sound wave ....................................................................................................... 1
2. Periodic Sine wave ............................................................................................ 2
3. Sampled Audio .................................................................................................. 3
4. CLASS AB vs. CLASS D ................................................................................... 5
5. Simplified H-bridge for a Class-AB amplifier....................................................... 6
6. Simplified H-bridge for a Class-D amplifier ......................................................... 7
7. H-Bridge Topology ............................................................................................. 8
8. Power Dissipation –CLASS D vs. CLASS AB .................................................... 9
9. Efficiency comparison CLASS AB vs. CLASS D ................................................ 9
10. Digital Pulse Modulation topology .................................................................. 11
11. Direct Digital Pulse Modulation topology ........................................................ 12
12. Practical Digital Pulse Modulation topology .................................................... 15
13. Interpolation ..................................................................................................... 15
14. 1st Order Noise Shaper .................................................................................. 16
15. STF & NTF of a 3rd order CIFB modulator ..................................................... 17
16. Direct PCM to PWM ...................................................................................... 18
17. Uniform AD double sided Modulation ............................................................. 19
18. Uniform AD single sided Modulation .............................................................. 20
19. H Bridge Power Stage ................................................................................... 22
20. Supply Noise on PWM .................................................................................. 23
21. Zobel Network ............................................................................................... 23
22. Digital CLASSD implementation showing major error source block ............... 25
23. MOSFET model for switching analysis ........................................................... 27
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Figure Page
24. Sidebands around the Audio Signal due to power supply noise .................... 31
25. SIMULINK result showing the noise overriding the clean PWM ..................... 31
26. Pulse Amplitude error due to finite switch impedance at high currents ........ 32
27. Feedback incorporating IMC principle ............................................................ 34
28. Noise Transfer Function of loop ..................................................................... 36
29. Pre-distortion block ......................................................................................... 37
30. Overall implementation of the IMC approach ................................................. 37
31. Control loop for Digital class D Amplifier ........................................................ 38
32. Timing Diagram of how the phases work? ..................................................... 39
33. Block level Implementation ............................................................................. 40
34. Direct Digital Feedback .................................................................................. 40
35. Analog part in the feedback ............................................................................ 42
36. Digital part in the feedback ............................................................................. 42
37. Digital Modulator Architecture ........................................................................ 44
38. Modulator Order vs. SNR ............................................................................... 45
39. Pole Zero Plot for NTF .................................................................................... 45
40. STF & NTF ..................................................................................................... 46
41. Zoomed in O/P spectrum with 22 KHz PCM audio input ................................ 46
42. Dynamically Scaled Coefficients .................................................................... 47
43. CIFB based Topology ..................................................................................... 49
44. UPWM based Double Sided Sampling .......................................................... 50
45. Implementation of UADD based DPWM ....................................................... 51
46. Duty cycle computed for the test case1 .......................................................... 52
47. PWM reconstructed using Computed duty ratios ........................................... 52
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Figure Page
48. Duty cycle computed for the test case 2 ......................................................... 53
49. PWM reconstructed using Computed duty ratio ............................................. 53
50. Spectrum of PWM o/p using UADD ............................................................. 54
51. Spectrum of PWM o/p using UADS ................................................................ 54
52. Simulink Model of Blanking delay generator .................................................. 55
53. Generated Blanking delay time domain & Frequency domain ...................... 56
54. Simulated MOSFET dissipation vs. Fsw ........................................................ 57
55. Power Stage Model in Simulink & Demodulation Filter .................................. 58
56. PWM with noise .............................................................................................. 59
57. CLASS D o/p with noise ................................................................................ 59
58. Different Feedback Strategies ........................................................................ 60
59. Open Loop Class D modeled in Simulink ....................................................... 61
60. Open Loop CLASS D performance (with PSR & PS-IMD) ............................. 62
61. PWM o/p with Power Stage Noise coupled ..................................................... 62
62. Feedback directly into the Digital Domain ..................................................... 63
63. Closed Loop Architecture .............................................................................. 63
64. Extracted Error Signal (PWM scaled_ SW- PWM ref) .................................... 64
65. Discretized Error Signal .................................................................................. 64
66. Pre distorted Input .......................................................................................... 65
67. Closed Loop CLASS D performance (with PSR & PS-IMD) .......................... 65
68. Block level of Feedback methodology ........................................................... 67
69. Duty Ratios calculated for PWM switch out .................................................... 68
70. Duty Ratios calculated for PWM modulator .................................................... 68
71. Duty Ratio error .............................................................................................. 69
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Figure Page
72. PWM Duty Ratio Calculator ............................................................................ 69
73. Plots of PS-IMD for Class D Model ............................................................... 70
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