Minimization of multiple-valued programmable logic array using simulated annealing.

76 Pages·0.83 MB·en_US

by  Earle, Robert C.;Butler, Jon T.;Yang, Chyan.

NAVAL POSTGRADUATE SCHOOL
Monterey, California
THESIS
MINIMIZATION OF MULTIPLE-VALUED
PROGRAMMABLE LOGIC ARRAY
USING SIMULATED ANNEALING
by
Robert C.Earle
December, 1991
Thesis Advisor: Jon T.Butler
Approved for public release; distribution is unlimited
T260062

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MinimizationofMultiple-ValuedProgrammableLogicArrayUsingSimulatedAnnealing
12 PERSONALAUTHOR(S) Earle,RobertCharles
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Master'sThesis From To December 1991 67
16 SUPPLEMENTARY NOTATION
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17 COSATICODES 18 SUBJECTTERMS(continueonreverseifnecessaryandidentifybyblocknumber)
FIELD GROUP SUBGROUP Multi-ValuedLogic; MinimizationHeuristics; PLADesign; SimulatedAnnealing
19 ABSTRACT(continueonreverseifnecessaryandidentifybyblocknumber)
Guaranteedminimalrealizationsofmulti-valuedprogrammablelogicarrayscanonlybeaccomplishedbyanexhaustivesearch. Exhaustive
searchisnotveryrealisticforcomplexexpressionsduetotheimmenseamountofCPUtimerequiredtoreachasolution. Tocircumvent
thisproblem,heuristicshavebeendeveloped. Theyprovidenear-minimalsolutions,butusesubstantiallylessCPUtime. Thisthesis
investigatesanewtypeofheuristicwhichisbuiltonthefoundationofsimpleimplicantoperationscontrolledbyanannealingprocess. This
newtypeofheuristicissuperiortoexistingheuristicswithrespecttominimizationcapabilitybutrequiresmoreCPUtime.
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Approved for public release; distribution is unlimited.
Minimization ofMultiple-Valued Programmable
Logic Array UsingSimulated Annealing
by
RobertC. Earle
Lieutenant United States Navy
,
B.S., United States Naval Academy, 985
1
Submitted in partial fulfillment
ofthe requirements for the degree of
MASTER OF SCIENCE IN ELECTRICAL ENGINEERING
from the
NAVAL POSTGRADUATE SCHOOL
December 1991
ABSTRACT
Guaranteedminimal realizationsofmulti-valuedprogrammablelogic arrays canonly
be accomplished by an exhaustive search. Exhaustive search is not very realistic for
complex expressions due to theimmense amount ofCPU timerequired to reach a solution.
To circumvent this problem, heuristics have been developed. They provide near-rninirnal
solutions, but use substantially less CPU time. This thesis investigates a new type of
heuristic which is built on the foundation of simple implicant operations controlled by an
annealing process. This new typeofheuristic is superior to existing heuristics with respect
to minimization capability but requires more CPU time.
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TABLE OF CONTENTS
I. INTRODUCTION
1
A BACKGROUND
1
B. NEW APPROACH
2
II. TWO NEW HEURISTICS
3
A. THE ANNEALING PROCESS
3
B. OPERATIONS
5
1 COMBINABILITY
5
2. ABSORBABILITY
6
3. DIVISION
7
ADJACENCY
4
. 8
5. CONSENSUS 10
6. RESHAPE n
C. HEURISTIC MECHANICS
12
1 . CUT & COMBINE !2
2. RESHAPE
13
III. EXPERIMENTAL RESULTS
15
A. ANNEALING PROCESS
15
B. PARAMETER ANALYSIS
18
IV