Microarchitecture of Network-on-Chip Routers: A Designer's Perspective

183 Pages·2015·5.814 MB·English

by  Giorgos Dimitrakopoulos, Anastasios Psarras, Ioannis Seitanidis (auth.)

Giorgos Dimitrakopoulos
Anastasios Psarras
Ioannis Seitanidis
Microarchitecture
of Network-on-
Chip Routers
A Designer's Perspective
Microarchitecture of Network-on-Chip Routers

Giorgos Dimitrakopoulos • Anastasios Psarras
Ioannis Seitanidis
Microarchitecture of
Network-on-Chip Routers
A Designer’s Perspective
123
GiorgosDimitrakopoulos AnastasiosPsarras
ElectricalandComputerEngineering ElectricalandComputerEngineering
DemocritusUniversityofThrace DemocritusUniversityofThrace
Xanthi,Greece Xanthi,Greece
IoannisSeitanidis
ElectricalandComputerEngineering
DemocritusUniversityofThrace
Xanthi,Greece
ISBN978-1-4614-4300-1 ISBN978-1-4614-4301-8(eBook)
DOI10.1007/978-1-4614-4301-8
SpringerNewYorkHeidelbergDordrechtLondon
LibraryofCongressControlNumber:2014945972
©SpringerScience+BusinessMediaNewYork2015
Thisworkissubjecttocopyright.AllrightsarereservedbythePublisher,whetherthewholeorpartof
thematerialisconcerned,specificallytherightsoftranslation,reprinting,reuseofillustrations,recitation,
broadcasting,reproductiononmicrofilmsorinanyotherphysicalway,andtransmissionorinformation
storageandretrieval,electronicadaptation,computersoftware,orbysimilarordissimilarmethodology
nowknownorhereafterdeveloped.Exemptedfromthislegalreservationarebriefexcerptsinconnection
with reviews or scholarly analysis or material supplied specifically for the purpose of being entered
and executed on a computer system, for exclusive use by the purchaser of the work. Duplication of
this publication or parts thereof is permitted only under the provisions of the Copyright Law of the
Publisher’slocation,initscurrentversion,andpermissionforusemustalwaysbeobtainedfromSpringer.
PermissionsforusemaybeobtainedthroughRightsLinkattheCopyrightClearanceCenter.Violations
areliabletoprosecutionundertherespectiveCopyrightLaw.
Theuseofgeneraldescriptivenames,registerednames,trademarks,servicemarks,etc.inthispublication
doesnotimply,evenintheabsenceofaspecificstatement,thatsuchnamesareexemptfromtherelevant
protectivelawsandregulationsandthereforefreeforgeneraluse.
While the advice and information in this book are believed to be true and accurate at the date of
publication,neithertheauthorsnortheeditorsnorthepublishercanacceptanylegalresponsibilityfor
anyerrorsoromissionsthatmaybemade.Thepublishermakesnowarranty,expressorimplied,with
respecttothematerialcontainedherein.
Printedonacid-freepaper
SpringerispartofSpringerScience+BusinessMedia(www.springer.com)
To Alexandros,Labros,and Marina
G.D.
To Yiannisand Aphrodite
A.P.
To Ioannisand Vassiliki
I.S.

Preface
Moderncomputingdevices, rangingfromsmartphonesand tablets up to powerful
servers, rely on complex silicon chips that integrate inside them hundreds or
thousandsofprocessingelements.Thedesignofsuchsystemsisnotaneasytask.
Efficientdesignmethodologiesareneededthatwouldorganizethedesigner’swork
and reduce the risk for a low-efficiency system. One of the main challenges that
the designer faces is how to connect the componentsinside the silicon chip, both
physicallyandlogically,withoutcompromisingperformance.Thenetwork-on-chip
(NoC) paradigmtries to answer this questionby applyingat the silicon chip level
well established networking principles, after suitably adapting them to the silicon
chip characteristics and to application demands. The routers are the heart and
the backbone of the NoC. Their main function is to route data from source to
destination, while they provide arbitrary connectivity between several inputs and
outputsthatallowstheimplementationofarbitrarynetworktopologies.
ThisbookfocusesonthemicroarchitectureofNoCroutersthattogether,withthe
networkinterfaces,executeall networkfunctionalities.The routersimplementthe
transportand physicallayers of the NoC, and their internalorganizationcritically
affectsthespeedofthenetworkintermsofclockfrequency,thethroughputofthe
networkintermsofhowmanypacketscanthenetworkserviceperclockcycleand,
thenetwork’sareaandenergyfootprintonthesilicondie.
Thegoalofthisbookistodescribethecomplexbehaviorofnetworkroutersina
compositional approach following simple construction steps that can be repeated
by any designer in a straightforward manner. The micro-architectural features
presentedinthisbookarebuiltontopofdetailedexamplesandabstractedmodels,
whennecessary,thatdonotleaveanydarkspotsontheoperationofthepresented
blocks and reveal the dependenciesbetween the differentparts of the router, thus
enabling any possible future optimization. The material of each chapter evolves
linearly,coveringsimplercasesbeforemovingtomorecomplexarchitectures.
Chapter1 gives an overview of network-on-chip design at the system level and
discusses the layeredapproachfollowed for transformingthe abstractread and
vii
viii Preface
write transactions between the modules of the system to actual bits that travel
in parallel on the links of the network finding their path towards their final
destination,usingtheroutersofthenetwork.
Chapter2 deals with link-level flow control policies and associated buffering
requirements for guaranteeing lossless and full throughput operation for the
communication of a single sender and receiver pair connected with a simple
point-to-pointlink.Thediscussionincludesbothsimpleready/validflowcontrol
aswellascredit-basedpoliciesunderaunifiedabstractflowcontrolmodel.The
behaviorof bothflowcontrolpolicieswhenusedin pipelinedlinksis analyzed
and analytical bounds are derived for each case. The chapter ends with the
packetization process and the enhancement needed to link-level flow control
policiesforsupportingmultiwordpackets.
Chapter3 departs from point-to-pointlinks and discusses in a step-by-step man-
ner the organization of many-to-one and many-to-many switched connections
supporting either simple or fully unrolled datapaths. The interplay between
arbitration,multiplexingandflowcontrolisanalyzedindetailusingbothcredits
andready/validprotocols.Thechapterendswith thedesignofafullwormhole
(or virtual-cutthrough)router that includesalso a routingcomputationmodule
thatallowsrouterstobeembeddedinarbitrarynetworktopologies.
Chapter4 departsfromroutermicroarchitectureanddescribesindetailthecircuit-
level organization of the arbiters and multiplexers used in the control and the
datapathoftherouters.Aunifiedapproachispresentedthatmergesalgorithmi-
cally the design ofarbitersthatemployvariousarbitrationpolicieswith thatof
multiplexingandallowsthedesignofefficientarbiterandmultiplexingcircuits.
Additionally,arbitersbuiltontopof2Drelativeprioritystatearealsodiscussed
indetail.
Chapter5 divesdeeperinthemicroarchitectureofawormholerouteranddiscusses
inacompositionalmannerthepipelinealternativesofwormholeroutersandtheir
implementation/performance characteristics. Multiple pipelined organizations
are derived based on two pipeline primitive modules. For each case, complete
running examples are given that highlight the pipeline idle cycles imposed by
the router’s structural dependencies, either across packets or inside packets of
the same input, and the way such dependencies are removed after appropriate
pipelinemodifications.
Chapter6 introduces virtual channels together with the flow control mechanism
and the bufferingarchitecturesneededto supporttheir operation.Virtualchan-
nels correspondto addinglanes to a street network thatallow cars(packets) to
utilize in a more efficient manner the available physical resources. Lanes are
added virtually and the packets that move in different lanes use the physical
channelsofthenetworkinatime-multiplexedmanner.Theinterplayofbuffering,
flow-control latencies and the chosen flow control mechanism (ready/valid or
credits) are analyzed in detail in this chapter and the requirements of each
configurationareidentified.
Chapter7 introducesthe microarchitectureof routers that connectlinks that sup-
port multiple virtual channels. The design of virtual-channel-based switching
Preface ix
connections begins from a simple many-to-one switching module and evolves
to a complete virtual-channel-basedrouter. The operation of a virtual-channel-
basedrouterinvolvesseveraltasksthatareanalyzedindetailtogetherwiththeir
dependenciesandtheirinteractionwiththeflow-controlmechanism.
Chapter8 builds on top of Chap.7 and presents the organization of high-speed
allocators that speedup significantly the operation of a baseline single-cycle
virtual-channel-basedrouter.Multiplealternativesarepresentedthatalloweither
the reduction of the needed allocation steps or their parallel execution that
effectivelyreducesthehardwaredelayoftherouter.
Chapter9 deals with the pipelined organization and microarchitecture of virtual-
channel-basedrouters.Thepipelinedconfigurationsofthevirtual-channel-based
routers are described in a modular manner, beginning from the description of
thestructureandoperationofthreeprimitivepipelinestages.Then,followinga
compositionalapproach,severalmulti-stagepipelinedconfigurationsarederived
by connectingthe presentedprimitivestagesin a plug-and-playmanner,which
helps in understandingbetter the operation of complex organizationsand their
associatedtiming-throughputtradeoffs.
Overall, we expect system, architecture, circuit, and EDA researchers and
developers,who are interestedin understandingthe microarchitectureof network-
on-chip routers, the associated design challenges, and the available solutions, to
benefitfromthematerialofthisbookandappreciatetheorderofpresentationthat
evolvesinastep-by-stepmanner,fromthebasicdesignprinciplestosophisticated
designtechniques.
Xanthi,Greece GiorgosDimitrakopoulos
June2014 AnastasiosPsarras
IoannisSeitanidis