Methods for multi-wire routing and apparatus implementing same

41 Pages·2013·2.83 MB·English

US007939443B2
(12) Ulllted States Patent (10) Patent N0.: US 7,939,443 B2
Fox et al. (45) Date of Patent: May 10, 2011
(54) METHODS FOR MULTI-WIRE ROUTING 2 I}; gufmg
AND APPARATUS IMPLEMENTING SAME 5,, 497,, 334 A 3/1996 Ruusjslemlalg eat al'
5,497,337 A 3/1996 P 311' t l.
(75) Inventors: Daryl Fox, Campbell, CA (US); Scott T. 5,581,098 A 12/1996 (£1,132; 1 e 3
Becker, Scotts Valley, CA (U S) 5,682,323 A 10/1997 Pasch et a1.
5,684,733 A 11/1997 Wu et a1.
(73) Assignee: Tela Innovations, Inc., Los Gatos, CA (Continued)
(Us)
FOREIGN PATENT DOCUMENTS
( * ) Not1ce: Subject' to any d1scla1mer, the term of this EP 1394858 3/2004
patent 1s extended or adjusted under 35 (Continued)
U.S.C. 154(b) by 300 days.
(21) Appl. N0.: 12/411,249 OTHER PUBLICATIONS
U.S. Appl. No. 60/625,342, ?led May 25, 2006, Pileggi et a1.
(22) Filed: Mar. 25, 2009 _
(Cont1nued)
(65) Prior Publication Data _
Primary Examiner * Chandra Chaudhan
Us 2009/0224408 A1 Sep' 10’ 2009 (74) Attorney, Agent, or Firm *Martine Penilla &
G 11 LLP
Related US. Application Data encare a’
(60) Provisional application No. 61/040,129, ?led on Mar. (57) ABSTRACT
27, 2008- A rectangular interlevel connector array (RICA) is de?ned in
a semiconductor chip. To de?ne the RICA, a virtual grid for
(51) Int‘ Cl‘ interlevel connector placement is de?ned to include a ?rst set
H011‘ 21/44 (200601) of parallel virtual lines that extend across the layout in a ?rst
(52) US. Cl. .............................. .. 438/599; 257/E21.575 direction’ and a Second Set ofparallel Vimlal lines that extend
(58) Field of Classi?cation Search ................ .. 438/588, across the layout in a second direction perpendicular to the
438/599, 926 ?rst direction. A ?rst plurality of interlevel connector struc
See application ?le fOr Complete Search history- tures are placed at respective gridpoints in the virtual grid to
_ form a ?rst RICA. The ?rst plurality of interlevel connector
(56) References Clted structures of the ?rst RICA are placed to collaboratively
connect a ?rst conductor channel in a ?rst chip level With a
US' PATENT DOCUMENTS second conductor channel in a second chip level. A second
4,197,555 A 4/1980 Uehara et a1. RICA can be interleaved With the ?rst RICA to collabora
21251 2 IBJya tively connect third and fourth conductor channels that are
436823202 A 7/1987 Tzgitzawa reflspectively interleaved With the ?rst and second conductor
5,121,186 A 6/1992 Wong et al. 0 anne 5
5,208,765 A 5/1993 Turnbull
5,224,057 A 6/1993 Igarashi 28 Claims, 25 Drawing Sheets
‘ 8033
1 /
// ____

US 7,939,443 B2
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7,338,896 B2 3/2008 Vanhaelemeersch et al. 2009/0024974 A1 1/2009 Yamada
7,350,183 B2 3/2008 Cui et al. 2009/0077524 A1 3/2009 Nagamura
7,353,492 B2 4/2008 Gupta et al. 2009/0106714 A1 4/2009 Culp et al.
7,360,179 B2 4/2008 Smith et al. 2009/0228853 A1 9/2009 Hong et al.
7,360,198 B2 4/2008 Rana et al. 2010/0006900 A1 1/2010 Becker et al.
7,366,997 B1 4/2008 Rahmat et al. 2010/0006986 A1 1/2010 Becker et al.
7,367,008 B2 4/2008 White et al. 2010/0011331 A1 1/2010 Becker et al.
7,383,521 B2 6/2008 Smith et al. 2010/0019308 A1 1/2010 Chan et al.
7,400,627 B2 7/2008 Wu et al. 2010/0023907 A1 1/2010 Becker et al.
7,404,173 B2 7/2008 Wu et al.
7,421,678 B2 9/2008 Barnes etal. FOREIGN PATENT DOCUMENTS
7,423,298 B2 9/2008 Mariyama et al. Ep 1670062 6/2006
7,424,694 B2 9/2008 Ikeda FR 2860920 4/2005
7,426,710 B2 9/2008 Zhang et JP 10_1 16911 5/1998
7,434,185 B2 10/2008 DOOllIlg et al. JP 2002_258463 9/2002
7,441,211 B1 10/2008 Gupta et al. JP 20051259913 9/2005
7,444,609 B2 10/2008 Charlebois et al. KR 10_1999_0057943 A 7/1999
7,446,352 B2 11/2008 Becker et al. KR 10_2000_0028830 A 5/2000
7,449,371 B2 11/2008 Kemerling et al. KR 10_2005_0030347 A 3/2005
7,458,045 B2 II/2008 Cote 6t W0 W0 Zoos/104356 II/ZOOS
7,465,973 B2 12/2008 Chang et al. W0 WO 2006/014849 2/2006
7,466,607 B2 12/2008 HplllS et al: W0 WO 2006/052738 5/2006
7,480,880 B2 1/2009 Visweswariah et al.
7,484,197 B2 1/2009 Allen et a1. OTHER PUBLICATIONS
7,487,475 B1 2/2009 Kriplani et a1.
7,506,300 B2 3/ 2009 Sezginer et al. Acar, et al., “A Linear-Centric Simulation Framework for Parametric
7509521 B2 3/2009 Melvln’ HI Fluctuations”, 2002, IEEE, Carnegie Mellon University USA, pp.
7,509,622 B2 3/2009 Sinha et a1. 1 8
7,514,959 B2 4/2009 Or-Bach et a1. ' ' _ _ _
7, 5 23 ,429 B2 4/2009 Kroyan et a1‘ AmaZawa, et al., “Fully PlanariZed Four-Level Intercormection with
7,563,701 B2 7/2009 Chang et a1, Stacked VLAS Using CMP of Selective CVD-Al and Insulator and
7,665,051 B2 2/2010 Ludwig et al. its Application to Quarter Micron Gate Array LSIs”, 1995, IEEE,
2007501112321 24:22.2 Japan,
1 eggl et ' Axelrad et a1. “Ef?cient Full-Chip Yield Analysis Methodology for
2003/0061592 A1 3/2003 Agrawal et al. OPC C t d VLSI D . ,, 2000 I t t. 1 S .
2003/0088842 A1 5/2003 Cirit _' Orrec e _ _ eslgn , , I1 efna 1011a ymposlum 011
2003/0229875 A1 12/2003 Smith et al. Quallty Electronlc DeS1gn<1$QED)~
2004/00497 54 A1 3/2004 Liao et a1, Balasinski et al. “Impact of Subwavelength CD Tolerance on Device
2004/0145028 A1 7/2004 Matsumoto et al. Performance”, 2002, SPIE.
2004/0153979 A1 55/2004 Chang Burkhardt, et al., “Dark Field Double Dipole Lithography (DDL) for
2004/0161878 A1 8/2004 Or'Bach et 31' Back-End-Of-Line Processes”, 2007, SPIE Proceeding Series, vol.
2004/0243966 A1 12/2004 Dellinger 6520, 65200K
2005/0055828 A1 3/2005 Wang et a1. ’ . 1 '“ b k i .th h .11 b1 .
Zoos/0087806 A1 400% Hokazono Capett-i, et a ., Su 1* 25 Li ograp y wit Dou e Patterning
2005/01011 12 A1 5 /200 5 Rueckes et a1‘ Technique for 45nm Technology Node Flash Memory Devices at)» I
2005/0136340 A1 6/2005 Baselmans et a1, 193nm”, 2007, SPIE Proceeding Series, vol. 6520; 65202K.
2005/0189614 A1 9/ 2005 Ihme etal. Chandra, et al., “An Interconnect Channel Design Methodology for
Zoos/0224982 A1 10/2005 Kemerllng et a1~ High Performance Integrated Circuits”, 2004, IEEE, Carnegie Mel
2005/0229130 A1 10/2005 Wu et al. lon Univ- ersit- y, pp. 1 _ 6.
2Z0o0o5s//00225618727516 AAl1 101//22000055 TRsoabil eest a1‘ Cheng, et al., “ Feasi.b i.l i. ty Study of Spli. tt.i ng Pi. tch Technology on
2006/0084261 A1 4/2006 Iwaki 45nm Contact Patterning with 0.93 N ”, 2007, SPIE Proceeding
2006/0101370 A1 5/2006 Cui et al. Sefles, V01~ 6520; 65202N~
2006/0112355 A1 5/2006 Pileggi et a1. Chow, et al., “The Design of a SRAM-Based Field-Programmable
2006/0121715 A1 6/2006 Chang et 81. Gate ArrayiPart II: Circuit Design and Layout”, 1999, IEEE, vol. 7
2006/0125024 A1 6/2006 IShigaki # 3 pp‘ 321330
2006/0151810 A1 7/2006 Ohshlge Clark et al. “Managing Standby and Active Mode Leakage Power in
2006/0181310 A1 8/2006 Rhee D S b M. D . ,, A 9 11 2004 ACM
2006/0197557 A1 9/2006 Chung eeP ‘1 ' JCT?“ eslgn ’ “gr _' ’ ’ '
2006/0206854 A1 9/2006 Barnes et a1‘ Cobb et al: Using OPC to Optimize for Image Slope and Improve
2006/0223302 A1 10/2006 Chang et a1. Process WIIIdOW”, 2003, SPIE
2007/0038973 A1 2/2007 Li et al. Devgan “Leakage Issues in IC Design: Part 3”, 2003, CCAD.
2007/0074145 A1 3/2007 Tanflka DeVor, et al., “Statistical Quality Design and Control”, 1992,
2007/0101305 A1 5/2007 Smith et a1‘ Macmillan Publishing Company, pp. 264-267.
2007/0106971 A1 5/2007 Llen et 31' Dusa, et al. “Pitch Doubling Through Dual Patterning Lithography
2007/0113216 A1 5/2007 Zhan- g Challenges i. n Integrati. on and Li. tho Budgets ,, , 2007, SPIE Proceed
2007/0209029 A1 9/2007 Ivonin et al. . S . 1 6520' 65200G
2007/0234252 A1 10/2007 Visweswariah et al. mg ‘mes’ ‘Y0 ~ ’ ~
2007/0256039 A1 1 H2007 White Bl-Gamal, Fast, Cheap and Under Control: The Next Implementa
2007/0274140 A1 11/2007 Joshi et 31‘ {ion Fabric”, Jun. 2-6, 2003, ACM Press, pp. 354-355.
Zoos/0005712 A1 1/2008 Charlebois et a1‘ Frankel, “Quantum State Control Interference Lithography and Trim
200g/0046g46 A1 Z/goog Chew et 31‘ Double Patterning for 32-16nm Lithography”, 2007, SPIE Proceed
2008/0098334 A1 4/2008 Pileggi et al. ing Series, Vol, 6520; 65202L,
2008/0127029 A1 5/2008 Graur et al. Garg, er a1 “Lithography Driven Layout Design”, 2005, IEEE,
2008/0144361 A1 6/2008 Wong Grobman et al. “Reticle Enhancement Technology Trends: Resource
2008/0148216 A1 6/2008 Chan et a1, and Manufacturability Implications for the Implementation of Physi
2008/0163141 A1 7/2008 Scheffer et al. cal Designs” Apr. 1-4, 2001, ACM.
2008/ 0168406 A1 7/ 2008 Rahmat et al. Grobman et al. “Reticle Enhancement Technology: Implications and
2008/0276105 A1 11/2008 Hoberman et al. Challenges for Physical Design” Jun. 18-22, 2001, ACM.
US 7,939,443 B2
Page 4
Gupta et al. “Enhanced Resist and Etch CD Control by Design Liu, et al., “Double Patterning with Multilayer Hard Mask Shrinkage
Perturbation”, Oct. 4-7, 2006, Society of Photo-Optical Instrumen for Sub-0.25 k1 Lithography”, 200, SPIE Proceeding Series, vol.
tation Engineers. 6520; 652021 , 2007.
Gupta et al. “A Practical Transistor-Level Dual Threshold Voltage Miller, “Manufacturing-Aware Design Helps Boost ICYield”, Sep. 9,
Assignment Methodology”, 2005, Sixth International Symposium 2004, http://www.ectimcs.com/showArticle.
on Quality Electronic Design (ISQED). jhtml?articleID:47102054.
Gupta et al. “Detailed Placement for Improved Depth of Focus and Mo, et al., “Checkerboard: A Regular Structure and its Synthesis,
CD Control”, 2005, ACM. International Workshop on Logic and Synthesis”, 2003, Department
Gupta et al. “Joining the Design and Mask Flows for Better and of Electrical Engineering and Computer Sciences, UC Berkeley,
Cheaper Masks”, Oct. 14-17, 2004, Society of Photo-Optical Instru California, pp. 1-7.
mentation Engineers. Mo, et al., “PLA-Based Regular Structures and Their Synthesis”,
Gupta et al. “Selective Gate-Length Biasing for Cost-Effective 2003, Department of Electrical Engineering and Computer Sciences,
Runtime Leakage Control”, Jun. 7-11, 2004, ACM. IEEE, pp. 723-729.
Gupta et al. “Wafer Topography-Aware Optical Proximity Correction Mo, et al., “Regular Fabrics in Deep Sub-Micron Integrated-Circuit
for Better DOF Margin and CD Control”, Apr. 13-15, 2005, SPIE. Design”, 2004, Kluwer Academic Publishers, Entire Book.
Hayashida, et al., “Manufacturable Local Interconnect technology Moore, Samuel K., “Intel 45-nanometer Penryn Processors Arrive,”
Fully Compatible with Titanium Salicide Process”, Jun. 11-12, 1991, Nov. 13, 2007, IEEE Spectrum, http://spectrum.ieee.org/semicon
VMIC Conference. ductors/design/intel-45nanometer-penryn-processors-arrive.
Heng, et al., “AVLSI Artwork Legalization Technique Base on a New Mutoh et al. “l-V Power Supply High-Speed Digital Circuit Tech
Criterion of Minimum Layout Perturbation”, 1997, ACM Press, pp. nology with Multithreshold-Voltage CMOS”, 1995, IEEE.
1 16-121. Op de Beek, et al., “Manufacturability issues with Double Patterning
Heng, et al., “Toward Through-Process Layout Quality Metrics”, for 50nm half pitch damascene applications, using RELACS® shrink
Mar. 3-4, 2005, Society of Photo-Optical Instrumentation Engineers. and corresponding OPC”, 2007, SPIE Proceeding Series, vol. 6520;
Hu, et al., “Synthesis and Placement Flow for Gain-Based Program 652001.
mable Regular Fabrics”, Apr. 6-9, 2003, ACM Press, pp. 197-203. Or-Bach, “Programmable Circuit Fabrics”, Sep. 18, 2001, e-ASIC,
Hutton, et al., “A Methodology for FPGA to Structured-ASIC Syn pp. 1-36.
thesis and Veri?cation”, 2006, EDAA, pp. 64-69. Otten, et al., “Planning for Performance”, DAC 1998, ACM Inc., pp.
Intel Core Microarchitecture White Paper “Introducing the 45 nm 122-127.
Next-Generation Intel Core Microarchitecture,” 2007, Intel Corpo Pack et al. “Physical & Timing Veri?cation of Subwavelength-Scale
ration. Designs-Part I: Lithography Impact on MOSFETs”, 2003, SPIE.
Jayakumar, et al., “A Metal and VIA Maskset Programmable VLSI Pandini, et al., “Congestion-Aware Logic Synthesis”, 2002, IEEE,
Design Methodology using PLAs”, 2004, IEEE, pp. 590-594. pp. 1-8.
Jhaveri, T. et al., MaximiZation of Layout Printability/Manufactur Pandini, et al., “Understanding and Addressing the Impact of Wiring
ability by Extreme Layout Regularity, Proc. of the SPIE, Apr. 2006. Congestion During Technology Mapping”, ISPD Apr. 7-10, 2002,
Kang, S.M., Metal-Metal Matrix (M3) for High-Speed MOS VLSI ACM Press, pp. 131-136.
Layout, IEEE Trans. on CAD, vol. CAD-6, No. 5, Sep. 1987. Patel, et al., “An Architectural Exploration of Via Patterned Gate
Kheterpal, et al., “Design Methodology for Manufacturability Based Arrays, ISPD 2003”, Apr. 6, 2003, pp. 184-189.
on Regular Logic-Bricks”, DAC, Jun. 13-17, 2005, IEEE/AMC, vol. Pileggi, et al., “Exploring Regular Fabrics to Optimize the Perfor
6520. mance-Cost Trade-Offs, Proceedings of the 40th ACM/IEEE Design
Kheterpal, et al., “Routing Architecture Exploration for Regular Fab Automation Conference (DAC) 2003”, Jun. 2003, ACM Press, pp.
rics”, DAC, Jun. 7-11, 2004, ACM Press, pp. 204-207. 782-787.
Kim, et al., “Double Exposure Using 193nm Negative Tone Poonawala, et al., “ILT for Double Exposure Lithography with Con
Photoresist”, 2007, SPIE Proceeding Series, vol. 6520; 65202M. ventional and Novel Materials”, 2007, SPIE Proceeding Series, vol.
Kim, et al., “Issues and Challenges of Double Patterning Lithography 6520; 65202Q.
in DRAM”, 2007, SPIE Proceeding Series, vol. 6520; 65200H. Qian et al. “Advanced Physical Models for Mask Data Veri?cation
Koorapaty, et al., “Exploring Logic Block Granularity for Regular and Impacts on Physical Layout Synthesis” 2003. IEEE.
Fabrics”, 2004, IEEE, pp. 1-6. Ran, et al., “An Integrated Design Flow for a Via-Con?gurable Gate
Koorapaty, et al., “Heterogeneous Logic Block Architectures for Array”, 2004, IEEE, pp. 582-589.
Via-Patterned Programmable Fabric”, 13th International Conference Ran, et al., “Designing aVia-Con?gurable Regular Fabric”, Custom
on Field Programmable Logic and Applications (FPL) 2003, Lecture Integrated Circuits Conference (CICC). Proceedings of the IEEE,
Notes in Computer Science (LNCS), Sep. 2003, Springer-Verlag, Oct. 2004, Oct. 1, 2004, pp. 423-426.
vol. 2778, pp. 426-436. Ran, et al., “On Designing Via-Con?gurable Cell Blocks for Regular
Koorapaty, et al., “Modular, Fabric-Speci?c Synthesis for Program Fabrics” Proceedings of the Design Automation Conference (DAC)
mable Architectures”, 12th International Conference on Field Pro 2004, Jun. 2004, ACM Press, s 198-203.
grammable Logic and Applications (FPLi2002, Lecture Notes in Ran, et al., “The Magic of aVia-Con?gurable Regular Fabric”, Pro
Computer Science (LNCS)), Sep. 2002, Springer-Verlag, vol. 2438 ceedings of the Tree International Conference on Computer Design
pp. 132-141. (ICCD) Oct. 2004.
Lavin et al. “Backend DAC Flows for “Restrictive Design Rules’”’, Ran, et al., “Via-Con?gurable Routing Architectures and Fast Design
2004, IEEE. Mappability Estimation for Regular Fabrics”, 2005, IEEE, pp. 25-32.
Li, et al., “A Linear-Centric Modeling Approach to Harmonic Bal Reis, et al., “Physical Design Methodologies for Performance Pre
ance Analysis”, 2002, IEEE, pp. 1-6. dictability and Manufacturability”, Apr. 14-16, 2004, ACM Press, pp.
Li, et al., “Nonlinear Distortion Analysis Via Linear-Centric Mod 390-397.
els”, 2003, IEEE, pp. 897-903. Robertson, et al., “The Modeling of Double Patterning Lithographic
Liebmann et al., “Integrating DFM Components Into a Cohesive Processes”, 2007, SPIE Proceeding Series, vol. 6520; 65200].
Design-To-Silicon Solution”, IBM Systems and Technology Group, Rovner, “Design for Manufacturability in Via Programmable Gate
b IBM Research, pp. 1-12. Arrays”, May 2003, Graduate School of Carnegie Mellon University.
Liebmann, et al., “High-Perfoimance Circuit Design for the RET Sengupta, “An Integrated CAD Framework Linking VLSI Layout
Enabled 65nm Technology Node”, Feb. 26-27, 2004, SPIE Proceed Editors and Process Simulators”, 1998, Thesis for Rice University,
ing Series, vol. 5379 pp. 20-29. pp. 1- 10 1 .
Liebmann, L. W., Layout Impact of Resolution Enhancement Tech Sengupta, et al., “An Integrated CAD Framework Linking VLSI
niques: Impediment or Opportunity?, International Symposium on Layout Editors and Process Simulators”, 1996, SPIE Proceeding
Physical Design, 2003. Series, vol. 2726; pp. 244-252.
US 7,939,443 B2
Page 5
Sherlekar, “Design Considerations for Regular Fabrics”, Apr. 18-21, Wilcox, et al., “Design for Manufacturability: A Key to Semiconduc
2004, ACM Press, pp. 97-102. tor Manufacturing Excellence”, 1998, IEEE, pp. 308-313.
Sreedhar et al. “Statistical Yield Modeling for Sub-Wavelength Wu, et al., “A Study of Process Window Capabilities for Two-dimen
Lithography”, 2008, IEEE. sional Structures under Double Exposure Condition”, 2007, SPIE
Stapper, “Modeling of Defects in Integrated Circuit Photolitho Proceeding Series, vol. 6520; 652020.
graphic Patterns”, Jul. 1, 1984, IBM, vol. 28 # 4, pp. 461-475. Xiong, et al., “The Constrained Via Minimization Problem for PCB
Taylor, et al., “Enabling Energy Ef?ciency in Via-Patterned Gate and VLSI Design”, 1988, ACM PRESS/IEEE, pp. 573-578.
Array Devices”, Jun. 7-11, 2004, ACM Press, pp. 874-877. Yamamaoto, et al., “New Double Expo sure Technique without Alter
Tian et al. “Model-Based Dummy Feature Placement for Oxide nating Phase Shift Mask”, 2007, SPIE Proceeding Series, vol. 6520;
ChemicaliMechanical Polishing Manufacturability” 2000, ACM.
652052P.
Tong, et al., “Regular Logic Fabrics for a Via Patterned Gate Array Yang, et al., “Interconnection DrivenVLSI Module Placement Based
(VPGA), Custom Integrated Circuits Conference”, Sep. 2003, Pro on Quadratic Programming and Considering Congestion Using LFF
ceedings of the IEEE, pp. 53-56. Principles”, 2004, IEEE, pp. 1243-1247.
Vanleenhove, et al., “A Litho-Only Approach to Double Patterning”, Yao, et al., “Multilevel Routing With Redundant Via Insertion”, Oct.
2007, SPIE Proceeding Series, vol. 6520; 65202F. 2006, IEEE, pp. 1148-1152.
Wang, et al., “Performance Optimization for Gridded-Layout Stan Zheng, et al.“Modeling and Analysis of Regular Symmetrically
dard Cells”, 2004, vol. 5567 SPIE. Structured Power/ Ground Distribution Networks”, DAC, Jun. 10- 14,
Wang, J. et al., Standard Cell Layout with Regular Contact Place 2002, ACM PRESS, pp. 395-398.
ment, IEEE Trans. on Semicon. Mfg., vol. 17, No. 3, Aug. 2004. Zhu, et al., “A Stochastic Integral Equation Method for Modeling the
Webb, Clair, “Layout Rule Trends and Affect upon CPU Design”, Rough Surface Effect on Interconnect Capacitance”, 2004, IEEE.
2006, vol. 6156 SPIE. Zhu, et al., “A Study of Double Exposure Process Design with Bal
Webb, Clair, “45nm Design for Manufacturing,” Intel Technology anced Performance Parameters for Line/ Space Applications”, 2007,
Journal, vol. 12, Issue 02, Jun. 17, 2008, ISSN 1535-864X, pp. SPIE Proceeding Series, vol. 6520; 65202H.
121-130. Zuchowski, et al., “A Hybrid ASIC and FPGA Architecture”, 2003,
Wenren, et al., “The Improvement of Photolithographic Fidelity of IEEE, pp. 187-194.
Two-dimensional Structures Though Double Exposure Method”,
2007, SPIE Proceeding Series, vol. 6520; 652021. * cited by examiner
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