Method and apparatus for preventing undesirable packet download with pending read/write ...

84 Pages·2013·4.39 MB·English

US007058065B2
United States Patent
(12) (10) Patent N0.: US 7,058,065 B2
Musoll et a]. (45) Date of Patent: Jun. 6, 2006
(54) METHOD AND APPARATUS FOR 5,023,776 A 6/1991 Gregor
PREVENTING UNDESIRABLE PACKET 5,121,383 A 6/1992 Golestani
DOWNLOAD WITH PENDING READ/VV RITE 5,291,481 A 3/1994 Doshi et a1~
OPERATIONS IN DATA PACKET 5,408,464 A 4/1995 Jurkevich
5,465,331 A 11/1995 Yan et a1.
PROCESSING 5,471,598 A 11/1995 Quaitgtromani et a1.
(76) Inventors: Enrique Musoll, 7210 V1a Romera, San 5,521,916 A 5/1996 Choudhury et a1.
Jose, CA (Us) 95139; Thomas Y_ Yeh, 5,559,970 A * 9/1996 Sharma .................... .. 710/317
10250 Danube Dr” cupeninoa CA (Us) 5,619,497 A 4/1997 Gallagher et al.
95014, Mario Nemirovsky, 19750 i ghagg ‘17:13:31
Northhampton Dr., Saratoga, CA (US) 536753790 A 10/1997 Wiggle e '
95070 5,708,814 A 1/1998 Short @1111.
( * ) Notice: Subject to any disclaimer, the term of this 5,724,565 A 3/1998 Dubey et a1~
patent is extended or adjusted under 35 i E0320 it 11'
U'S'C' 154(1)) by 812 days‘ 5,, 784,, 699 A 7/1998 Meei /1u8r1 1e0 11a e. t a1.
(21) Appl. N0.: 09/924,755 5,796,966 A 8/1998 Simcoe et a1.
5,809,321 A 9/1998 Hansen et a1.
(22) Filed: Aug. 7, 2001
(Continued)
(65) Prior Publication Data OTHER PUBLICATIONS
Us 2002/0039368 A1 Apr‘ 4’ 2002 U.S. Appl. No. 09/737,375, Mario Nemirovsky et a1.
Related US. Application Data
(63) Continuation-in-part of application No. 09/737,375, (Commued)
?led 011 1360- 14, 2000- Primary ExamineriAfsar Qureshi
(60) Provisional application No. 60/181,364, ?led on Feb.
8, 2000. (57) ABSTRACT
(51) Int. Cl.
H04L 12/56 (2006-01) A logic system for resolving port contentions associated
G06F 13/00 (2006-01) With memory-access requests in data packet routing is
(52) US. Cl. ................. .. 370/395.7; 370/413; 370/428; provided. The logic system comprises a determination logic
710/52; 711/170 for assessing and reporting port status of busy or not busy,
(58) Field of Classi?cation Search .............. .. 370/360, 21 Command mechanism for issuing Commands contingent on
370/379, 3957 412, 3814383, 39572; 710/52, determination results and a staged buffer memory for hold
710/310, 22’ 127, 154; 711/154, 127, 170 ing pending requests Waiting for permission to access the
See application ?le for Complete Search history, memory. A single request at the head of the buiTer memory
is considered for port access whereupon if a port is deter
(56) References Cited mined to be busy, the command logic issues appropriate
commands to units responsible for downloading packets
U.S. PATENT DOCUMENTS from the memory and for sending neW memory-access
requests.
4,200,927 A 4/1980 Hughes et a1.
4,707,784 A ll/l987 Ryan et a1.
4,942,518 A 7/1990 Weatherford et a1. 10 Claims, 55 Drawing Sheets
Network/Switclnng Fabric Interface %
D1evlc
';
0
203 j
215
q Network Our
117 Deviceid 4141mm
0m Buffer’
Local Packet
system
Stream Processing Unit Register Transfer Unit (RTU) SCRAAMM
(5110) 229 227
CCID‘EXB ,/
US 7,058,065 B2
Page 2
US. PATENT DOCUMENTS Musoll et al., “Mechanism to Over?ow Packets to a Soft
ware Controlled Memory When They Do Not Fit into a
5,812,810 A 9/1998 Sager
Hardware Controlled Memeory,”, Jul. 3, 2001, Disclosure
5,892,966 A 4/1999 Petrick et al.
Document #496391.
5,918,050 A 6/1999 Rosenthal et al.
5,978,570 A 11/1999 Hillis Musoll et al., “Mechanism for Allowing a Limited Packet
5,978,893 A 11/1999 Bakshi et a1. Head and/or Tail Growth Without Moving the Packet to a
5,987,578 A 11/1999 Butcher Different Memeory Location,” Apr. 16, 2001, Disclosure
6,009,516 A 12/1999 Steiss et al. Document #492429.
6,016,308 A 1/2000 Crayford et al. Musoll et al., Mechanism to Activate a Context When No
6,023,738 A 2/2000 Priem et a1. Stream is Running in a Multi-Streaming Processing Core,:
6,047,122 A 4/2000 Spiller
Apr. 16, 2001, Disclosure Document #492431.
6,070,202 A 5/2000 Minkolf et al.
Musoll, Enric, “Functional Validation of a Packet Manage
6,073,251 A 6/2000 Jewett et al.
ment Unit,” May 18, 2001, Disclosure Document #429011.
6,088,745 A 7/2000 Bertagna et al.
6,131,163 A 10/2000 Wiegel Sampath et al., “Mechanism to Un-speculatively Pre-fetch
6,151,644 A 11/2000 Wu Instructions from the Thread Associated to a Packet,” Apr. 2,
6,157,955 A 12/2000 Narad et a1. 2001, Disclosure Document #491527.
6,169,745 B1 1/2001 Liu et al. Yamamoto, Wayne. An Analysis of Multistreamed,
6,219,339 B1 4/2001 Doshi et a1. Superscalar Processor Architectures. University of Califor
6,219,783 B1 4/2001 Zahir et al. nia Santa Barbara Dissertation. Dec. 1995. Santa Barbara,
6,223,274 B1 4/2001 Catthoor et a1. US.
6,226,680 B1 5/2001 Boucher et al. Yamamoto et al. “Increasing Superscalar Performance
6,247,105 B1 6/2001 Goldstein et a1. Through Multistreaming.” Parallel Architectures and Com
6,249,801 B1 6/2001 Zisapel et al. pilation Techniques (PACT ’95). 1995.
6,253,313 B1 6/2001 Morrison et al.
The PowerPC Architecture: A Speci?cation for a New
6,263,452 B1 7/2001 Jewett et al.
Family of RISC Processors. 2nd Ed. May 1994. pp. 70-72.
6,381,242 B1 4/2002 Maher, III et al.
6,389,468 B1 5/2002 Muller et al. Morgan Kaufmann. San Francisco, US.
6,438,135 B1 8/2002 TZeng MC68020 32-Bit Microprocessor User’s Manual. 3rd Ed..
6,453,360 B1 9/2002 Muller et al. 1989. pp. 3-125, 3-126, and 3-127. Prentice Hall, NJ, US.
6,460,105 B1 10/2002 Jones et al. Potel, M. J. “Real-Time Playback in Animation Systems.”
6,483,804 B1 11/2002 Muller et al. Proceedings of the 4th Annual Conference on Computer
6,502,213 B1 12/2002 Bowman-Amuah Graphics and Interactive Techniques. 1977. pp. 72-77. San
6,523,109 B1 2/2003 Meier
Jose, CA, US.
6,529,515 B1 3/2003 Raz et al.
ARM Architecture Reference Manual. 1996. pp. 3-41, 3-42,
6,535,905 B1 3/2003 Kalafatis et al.
3-43, 3-67, and 3-68. Prentice Hall, NJ, US.
6,614,796 B1 * 9/2003 Black et al. .............. .. 370/403
6,625,808 B1 9/2003 Tarditi ESA/390 Principles of Operation. IBM Online Publications
6,640,248 B1 10/2003 Jorgensen Center Reference No. SA22-7201-08. Table of Contents and
6,650,640 B1 11/2003 Muller et al. paras. 7.5.31 and 7.5.70. IBM Corporation. Boulder, CO,
6,738,371 B1 5/2004 Ayres US.
6,738,378 B1 5/2004 Tuck, III et al. MC88110 Second Generation RISC Microprocessor User’s
6,813,268 B1 11/2004 Kalkunte et al. Manual. 1991. pp. 10-66, 10-67, and 10-71. Motorola, Inc.
2001/0004755 A1 6/2001 Levy et a1.
Diefendorlf et al. “Organization of the Motorola 88110
2001/0005253 A1 6/2001 Komatsu
Superscalar RISC Microprocessor.” IEEE Journal of Micro
2001/0024456 A1 9/2001 Zaun et 31.
2001/0043610 A1 11/2001 Nemirovsky et 31. electronics. Apr. 1992. pp. 40-63. vol. 12, No. 2. IEEE. New
2001/0052053 A1 12/2001 Nemirovsky et a1. York, NY, US.
2002/0016883 A1 2/2002 Musoll et a1. Kane, Gerry. PA-RISC 2.0 Architecture. 1996, pp. 7-106 and
2002/0049964 A1 4/ 2002 Takayama et al. 7-107. Prentice Hall. NJ, US.
2002/0054603 A1 5/2002 Musoll et a1. Diefendorlf et al. “AltiVec Extension to PowerPC Acceler
2002/0071393 A1 6/2002 Musoll ates Media Processing.” IEEE Journal of Microelectronics.
2002/0083173 A1 6/2002 Musoll et a1.
vol. 20, No. 2 (2000): pp. 85-95.
2002/0124262 A1 9/2002 Basso et a1.
Grunewald et al. “Towards Extremely Fast Context Switch
2004/0015598 A1 1/2004 Jin-Fun
ing in a Block Multithreaded Processor.” Proceedings of
2004/0148382 A1 7/2004 Narad et a1.
EUROMICRO 22, 1996. pp. 592-599.
2004/0172471 A1 9/2004 Porter
2004/0172504 A1 9/2004 BalaZich et 31. Bradford et al. “Efficient Synchronization for Multithreaded
2004/0213251 A1 10/2004 Tran et al. Processors.” Workshop on Multithreaded Execution, Archi
2005/0061401 A1 3/2005 Tokoro et al. tecture, and Compilation. Jan-Feb. 1998. pp. 1-4.
Pai et al. “An Evaluation of Memory Consistency Models
OTHER PUBLICATIONS
for Shared-Memory Systems with ILP Processors.” Pro
U.S. Appl. No. 09/608,750, Nemirovsky et al. ceedings ofASPLOS-VII, Oct. 1996: pp. 12-23, ACM, Inc.
US. Appl. No. 09/602,279, Nemirovsky et al. YoaZ et al. “Speculation Techniques for Improving Load
Melvin et al., “Extended Instruction Set for a Packet Pro Related Instruction Scheduling.” 1999. pp. 42-53, IEEE.
cessing Applications,” Jul. 5, 2001, Disclosure Document Kessler, R. E. “The Alpha 21264 Microprocessor: Out-of
#496559. Order Execution at 600 MHZ.” Aug. 1998.
Musoll et al., “Hardware Algorithm for Allocating and Donalson et al. “DISC: Dynamic Instruction Stream Com
De-Allocating Consecutive Blocks of Memory,” Apr. 3, puter, An Evaluation of Performance.” 26th Hawaii Confer
2001, Disclosure Document #491557. ence on Systems Sciences. vol. 1. 1993. pp. 448-456.
US 7,058,065 B2
Page 3
Nemirovsky et al. “DISC: Dynamic Instruction Stream Dynamic Storage Allocation”, 1997, pp. 435-458, Addison
Computer.” ACM. 1991. pp. 163-171. Wesley, US.
Ungerer et al. A Survey of Processors With Explicit * Diefendorff, Keith, K7 Challenges Intel, Microprocessor
Multithreading. ACM Computing Surveys, VOl., 35, No. 1,
Report, Oct. 26, 1998, VOl. 12, No. 14, US.
Mar. 2003. pp. 29-63.
US. Appl. No. 09/591510, ?led Jun. 12, 2000, Gelinas et al.
* Knuth, Donald E., “The Art of Computer Programming,
Third Edition, VOl. 1, Fundamental Algorithms”, “Sec. 2.5 * cited by examiner
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