Memory architecture exploration for programmable embedded systems

147 Pages·2003·5.138 MB·English

by  Peter Grun, Nikil Dutt, Alexandru Nicolau

Memory Architecture Exploration
for Programmable Embedded Systems
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MEMORY ARCHITECTURE
EXPLORATION FOR PROGRAMMABLE
EMBEDDED SYSTEMS
PETER GRUN
Center for Embedded Computer Systems,
University of California, Irvine
NIKIL DUTT
Center for Embedded Computer Systems,
University of California, Irvine
ALEX NICOLAU
Center for Embedded Computer Systems,
University of California, Irvine
KLUWER ACADEMIC PUBLISHERS
NEW YORK,BOSTON, DORDRECHT, LONDON, MOSCOW
eBookISBN: 0-306-48095-6
Print ISBN: 1-4020-7324-0
©2002 Kluwer Academic Publishers
NewYork, Boston, Dordrecht, London, Moscow
Print ©2003 Kluwer Academic Publishers
Dordrecht
All rights reserved
No part of this eBook maybe reproducedor transmitted inanyform or byanymeans,electronic,
mechanical, recording, or otherwise, without written consent from the Publisher
Created in the United States of America
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Contents
List of Figures ix
List of Tables xiii
Preface xv
Acknowledgments
1. INTRODUCTION 1
1.1 Motivation 1
1.2 Memory Architecture Exploration for Embedded Systems 2
1.3 Book Organization 7
2. RELATED WORK 9
2.1 High-Level Synthesis 9
2.2 Cache Optimizations 10
2.3 Computer Architecture 11
2.4 Disk File Systems 12
2.5 Heterogeneous Memory Architectures 13
2.5.1 Network Processors 14
2.5.2 Other Memory Architecture Examples 15
2.6 Summary 16
3. EARLY MEMORY SIZE ESTIMATION 17
3.1 Motivation 17
3.2 Memory Estimation Problem 18
3.3 Memory Size Estimation Algorithm 20
3.3.1 Data-dependence analysis 22
3.3.2 Computing the memory size between loop nests 23
3.3.3 Determining the bounding rectangles 23
vi MEMORY ARCHITECTURE EXPLORATION
3.3.4 Determining the memory size range 24
3.3.5 Improving the estimation accuracy 25
3.4 Discussion on Parallelism vs. Memory Size 25
3.5 Experiments 27
3.6 Related Work 28
3.7 Summary 29
4. EARLY MEMORY AND CONNECTIVITY
ARCHITECTURE EXPLORATION 31
4.1 Motivation 31
4.2 Access Pattern Based Memory Architecture Exploration 32
4.2.1 Our approach 32
4.2.2 Illustrative example 34
4.2.3 The Access Pattern based Memory Exploration (APEX)
Approach 37
4.2.3.1 Access Pattern Clustering 37
4.2.3.2 Exploring Custom Memory Configurations 39
4.2.4 Experiments 39
4.2.4.1 Experimental Setup 40
4.2.4.2 Results 41
4.2.5 Related Work 45
4.3 Connectivity Architecture Exploration 46
4.3.1 Our approach 47
4.3.2 Illustrative example 48
4.3.3 Connectivity Exploration Algorithm 51
4.3.3.1 Cost, performance, and power models 55
4.3.3.2 Coupled Memory/ConnectivityExplorationstrategy 57
4.3.4 Experiments 59
4.3.4.1 Experimental Setup 59
4.3.4.2 Results 60
4.3.5 Related Work 72
4.4 Discussion on Memory Architecture 74
4.5 Summary and Status 75
5. MEMORY-AWARE COMPILATION 79
5.1 Motivation 79
5.2 Memory Timing Extraction for Efficient Access Modes 80
5.2.1 Motivating Example 81
5.2.2 Our Approach 83
Contents vii
5.2.3 TIMGEN: Timing extraction algorithm 84
5.2.4 Experiments 89
5.2.4.1 Experimental Setup 89
5.2.4.2 Results 90
5.2.5 Related Work 92
5.3 Memory MissTraffic Management 94
5.3.1 Illustrative example 95
5.3.2 Miss Traffic Optimization Algorithm 98
5.3.3 Experiments 101
5.3.3.1 Experimental setup 102
5.3.3.2 Results 102
5.3.4 Related Work 105
5.4 Summary 107
6. EXPERIMENTS 109
6.1 Experimental setup 109
6.2 Results 110
6.2.1 The Compress Data Compression Application 110
6.2.2 The Li Lisp Interpreter Application 114
6.2.3 The Vocoder Voice Coding Application 116
6.3 Summary of Experiments 117
7. CONCLUSIONS 119
7.1 Summary of Contributions 119
7.2 Future Directions 120
References 121
Index
127
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List of Figures
1.1 The interaction between the Memory Architecture, the
Application and the Memory-Aware Compiler 3
1.2 Our Hardware/Software Memory Exploration Flow 5
2.1 Packet Classification in Network Processing 14
3.1 Our Hardware/Software Memory Exploration Flow 18
3.2 The flow of MemoRex approach 21
3.3 Outline of the MemoRex algorithm. 21
3.4 Illustrative Example 22
3.5 Memory estimation for the illustrative example 24
3.6 (a) Accuracy refinement, (b) Complete memory trace 24
3.7 Input Specification with parallel instructions 26
3.8 Memory behavior for example with sequential loop 26
3.9 Memory behavior for example with forall loop 26
3.10 Memory Size Variation during partitioning/parallelization
29
4.1 The flow of our Access Pattern based Memory Explo-
ration Approach (APEX). 33
4.2 Memory architecture template. 34
4.3 Example access patterns. 35
4.4 Self-indirect custom memory module. 36
4.5 Access Pattern Clusteringalgorithm. 38
4.6 Exploration algorithm. 40
4.7 Miss ratio versus cost trade-off in Memory Design Space
Exploration for Compress (SPEC95) 42