Low power/low voltage techniques for analog CMOS circuits

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Low power/low voltage techniques for analog CMOS circuits
Cassia, Marco
Publication date:
2004
Document Version
Early version, also known as pre-print
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Citation (APA):
Cassia, M. (2004). Low power/low voltage techniques for analog CMOS circuits. Technical University of
Denmark.

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LOW POWER / LOW VOLTAGE
TECHNIQUES FOR
ANALOG CMOS CIRCUITS
MarcoCassia
Thisthesisissubmittedinpartialful(cid:2)llment
oftherequirementsforobtaining thePh.D.degreeat:
(cid:216)rsted DTU
(cid:15)
TechnicalUniversityofDenmark(DTU)
31July,2004

ABSTRACT
Thisworkpresentstwoseparatestudycasestoshedlightonthedifferentaspectsoflow-power
andlow-voltagedesign.
In the (cid:2)rst example, a low-voltage folded cascode operational transconductance ampli(cid:2)er was
designed to achieve 1-V power supply operation. This is made possible by a novel current driven
bulk (CDB) technique, which reduces the MOST threshold voltage by forcing a constant current
thoughthetransistorbulkterminal. AprototypewasfabricatedinastandardCMOSprocess;mea-
surementsshowa69-dBdcgainovera2-MHzbandwidth,andcompatibleinput-andoutputvoltage
levelsata1-Vpowersupply. LimitationsandimprovementsofthisCDBtechniquearediscussed.
The second part of the work is concerned with analog RF circuits. A previously unknown
intrinsic non-linearity of standard (cid:6)(cid:1) fractional-N synthesizers is identi(cid:2)ed. A general analytical
modelfor(cid:6)(cid:1)fractional-Nphased-lockedloops(PLLs)thatincludestheeffectofthenon-linearity
is derived and an improvement to the standard synthesizer topology is discussed. Also, a new
methodology for behavioral simulation is presented: the proposed methodology is based on an
object-oriented event-driven approach and offers the possibility to perform very fast and accurate
simulations; the theoretical models developed validate the simulation results. A study case for
EGSM/DCSmodulationisusedtodemonstratetheapplicabilityofthesimulationmethodologyto
theanalysisofrealsituations.
A novel method to calibrate the frequency response of a Phase-Locked Loop concludes the
research. The method requires just an additional digital counter to measure the natural frequency
ofthePLL;moreoveritiscapableofestimatingthestaticphaseoffset. Themeasuredvaluecanbe
usedtotunethePLLresponsetothedesiredvalue. Themethodisdemonstratedmathematicallyon
atypicalPLLtopologyanditisextendedto(cid:6)(cid:1)fractional-NPLLs.
iii

RESUM(cid:201)
I afhandlingen pr(cid:230)senteres to forskellige case studies til belysning af forskellige aspekter ved
lowpower/lowvoltagedesign.
Det fłrste case study omhandler en lavsp(cid:230)ndings foldet kaskode transkonduktans operations-
forst(cid:230)rker, konstrueret til at fungere ved en forsyningssp(cid:230)nding p(cid:229) 1V. Dette er muliggjort ved
anvendelse af en ny forsp(cid:230)ndingsteknik, hvor transistorens bulkterminal kontrolleres med en kon-
stant strłmi lederetningen. Herved reducerestransistorenst(cid:230)rskelsp(cid:230)nding. Der er fremstilleten
prototype i en standard CMOS teknologi, og m(cid:229)linger viser en forst(cid:230)rkning p(cid:229) 69dB, en b(cid:229)nd-
breddep(cid:229)2MHzogkompatibleindgangsogudgangsspndingervedenforsyningssp(cid:230)ndingp(cid:229)1V.
Begr(cid:230)nsningerogforbedringerveddenudvikledeforsp(cid:230)ndingsmetodediskuteres.
Det andet case study omhandler RF kredslłb. En ikke tidligere beskrevet intrinsisk ulinearitet
ved en standard Sigma-Delta fractional-N synt hesizer er blevet identi(cid:2)ceret. Der er udviklet en
generelanalytiskmodelforenSigma-Deltafractional-Nfasel(cid:229)stkreds(PLL)somtagerhensyntil
denne ulinearitet, og der er foresl(cid:229)et en forbedring af den normale synthesizer topologi. Der er
endviderepr(cid:230)senteretennymetodetilsystemsimuleringafdetfasel(cid:229)stesystem. Dennesimulering
anvenderenobjektorienteret,event-drivenmetodeoggivermulighedformegethurtigeognłjagtige
simuleringer. Metodenerdemonstreretp(cid:229)etpraktiskeksempeltilEGSM/DCSmodulation.
Forskningsarbejdet omhandler til slut en ny metode til kalibrering af frekvenskarakteristik for
en fasel(cid:229)st slłjfe. Denne metode kr(cid:230)ver blot en ekstra digital t(cid:230)ller til m(cid:229)ling af PLL’ens egen-
frekvens. Metodenkanogs(cid:229)anvendestilenestimeringafdetstatiskefase-offset. Dem(cid:229)ltev(cid:230)rdier
kanbenyttestilentuningafPLLkarakteristikkentildenłnskedev(cid:230)rdi. Metodeneftervisesmatem-
atiskp(cid:229)enstandardPLLtopologiogudvidesdereftertilanvendelsep(cid:229)enSigma-Deltafractional-N
PLL.
v
ACKNOWLEDGMENTS
This Ph. D. project was carried out at (cid:216)rsted DTU, Technical University of Denmark, under
(cid:15)
thesupervisionofprofessorErikBruun,(cid:216)rsted DTU.Itwas(cid:2)nancedbyascholarshipfromDTU.
(cid:15)
I would like to express my gratitude to everyone that have helped and supported me over the
last three years. First of all I would like to thank my supervisor Erik Bruun for making the study
possibleandforhisguidance. ForCADsupport,OSsetupandseveralotherpracticalissues,thanks
toAllanJłrgensenforhisabilityinmakingthingsrunsmoother.
SpecialthanksareduetomygoodfriendPeterShahforarrangingmystayingatQualcommand
forhissupervision. IalsowouldliketothankalltheQCTdepartmentofQualcomm,SanDiegofor
thegreatsupportduringtheinternship.
Fortheproofreadingeffortofthisthesisandfortheseveraltechnicaldiscussions, mydeepest
gratitudegoestomycolleagueandfriendJannikH.Nielsen. Finally,Iwouldliketoacknowledge
mybrotherFabioforthe(cid:2)nalreadings.
vi
CONTENTS
1 Introduction 1
I LowVoltageAmpli(cid:2)er 5
2 Limitstolow-voltagelow-powerdesign 7
2.1 Low-voltagesupplylimits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thresholdvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Sub-thresholdregion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Transistorspeed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5 Powerlimitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6 Analogswitches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.7 Transistorstackingandcascoding. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.8 Dynamicrange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.9 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 CMOSbulktechniquesforLow-Voltageanalogdesign 13
3.1 Bulk-drivenMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 MOSthresholdvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.1 DTMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 Current-DrivenBulkapproach . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4 CurrentDrivenBulkMOS 19
4.1 CDBMOSanalysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1.1 Outputimpedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1.2 Parasiticcapacitances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1.3 Slew-rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1.4 Frequencybehavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1.4.1 Increasedbiascurrents . . . . . . . . . . . . . . . . . . . . . . 25
4.1.4.2 Cascodetransistor . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1.4.3 Decouplingcapacitor. . . . . . . . . . . . . . . . . . . . . . . . 25
4.1.5 Parasiticbipolargain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2 CDBnoiseperformance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2.1 Supplynoisecoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.3 CDBMOSsummary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5 1VOperationalTransconductanceAmpli(cid:2)er 31
5.1 OTAarchitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
vii
viii CONTENTS
5.2 OTAsimulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.2.1 Frequencyresponse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.3 Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.4 Analysisofthemeasureddata . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.5 Sub-1Vsupplyvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.6 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
II (cid:6)(cid:1)synthesizer 43
6 (cid:6)(cid:1)SynthesizersTheory 45
6.1 Phase-LockedLoop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.2 Fractional-Nsynthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.3 (cid:6)(cid:1)fractional-NPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.3.1 (cid:6)(cid:1)modulatorperformance . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.4 S/H(cid:6)(cid:1)FractionalN spuriousperformance . . . . . . . . . . . . . . . . . . . . . 53
6.5 S/H(cid:6)(cid:1)FractionalN PLLtopology . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.6 Linearmodelderivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.6.1 Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.7 Analyticalevaluationoftheintrinsicnon-linearity . . . . . . . . . . . . . . . . . 61
6.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7 (cid:6)(cid:1)PLLssimulationtechnique 65
7.1 Event-drivenobjectorientedmethodology . . . . . . . . . . . . . . . . . . . . . . 65
7.2 SimulationCore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
7.2.1 VCOmodel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.2.2 Loop(cid:2)ltermodel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
7.3 VerilogImplementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.4 Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
8 (cid:6)(cid:1)synthesizersfordirectGSMmodulation 79
8.1 Transmitterarchitectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
8.2 SystemarchitectureforEGSM/DCS . . . . . . . . . . . . . . . . . . . . . . . . . 81
8.3 Modulationaccuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
8.4 Designexample . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
8.4.1 Impactofnon-linearitiesonthesynthesizerperformance. . . . . . . . . . . 86
9 Calibration 91
9.1 Measurementscheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
9.2 Mathematicalderivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
CONTENTS ix
9.3 Estimationofthestaticphaseoffset . . . . . . . . . . . . . . . . . . . . . . . . . 96
9.4 Extensionto(cid:6)(cid:1)PLLtopologies . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
9.5 Simulationresults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
9.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
10 Conclusions 103
III Appendices 105
A Verilogcode 107
B Oscillationfrequencyestimation 117
C Publications 125