Low-Power Stereo Audio DAC With Stereo Class-D Speaker Amplifier (Rev. A)

100 Pages·2016·1.4 MB·English

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TLV320DAC3101
SLAS666B–JANUARY2010–REVISEDOCTOBER2018
Low-Power Stereo Audio DAC With Audio Processing
and Stereo Class-D Speaker Amplifier
1 Introduction
1.2 Applications
1.1 Features
• PortableAudioDevices
• StereoAudioDACWith95-dB SNR
• MobileInternetDevices
1
• Supports8-kHzto192-kHzSampleRates
• e-Books
• Stereo1.29-WClass-D BTL8-Ω SpeakerDriver
WithDirect BatteryConnection
1.3 Description
• 25Built-InProcessingBlocks(PRB_P1 –
PRB_P25)ProvidingBiquadFilters,DRC,and3D The TLV320DAC3101 device is a low-power,
• DigitalSine-WaveGeneratorforBeepsandKey- highly integrated, high-performance DAC with
Clicks(PRB_P25) selectable digital audio processing blocks and
• User-ProgrammableBiquadandFIRFilters 24-bitstereoplayback.
• TwoSingle-EndedInputsWithMixingandOutput
The device integrates headphone drivers and
LevelControl
speaker drivers. The TLV320DAC3101 device
• StereoHeadphoneorLineoutandClass-D
has a suite of built-in processing blocks for
SpeakerOutputsAvailable
digital audio processing. The digital audio data
• MicrophoneBias
format is programmable to work with popular
• HeadphoneDetection audio standard protocols (I2S, left-justified, and
• DigitalMixingCapability right-justified) in master, slave, DSP, and TDM
• PinControlorRegisterControlforDigital-Playback modes. Bass boost, treble, or EQ is supported
Volume-ControlSettings by the programmable digital signal-processing
• ProgrammablePLLforFlexibleClockGeneration block. An on-chip PLL provides the high-speed
• I2S, Left-Justified,Right-Justified,DSP,andTDM clock needed by the digital signal-processing
AudioInterfaces block. The volume level is controlled by either
• I2CControlWithRegisterAuto-Increment pin control or by register control. The audio
• FullPower-DownControl functions are controlled using the I2C serial
• PowerSupplies: bus.
– Analog:2.7 V–3.6V
The TLV320DAC3101 device has a
– DigitalCore:1.65V–1.95V
programmable digital sine-wave generator and
– DigitalI/O:1.1V–3.6V
isavailableina32-pinQFNpackage.
– Class-D: 2.7 V–5.5V(SPLVDDandSPRVDD ≥
AVDD) DeviceInformation(1)
• 5-mm×5-mm32-QFNPackage
PARTNUMBER PACKAGE BODYSIZE
TLV320DAC3101 QFN(RHB) 5.00mmx5.00mm
(1) Formoreinformation,see,Mechanical,Packaging,and
OrderableInformation.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.
TLV320DAC3101
SLAS666B–JANUARY2010–REVISEDOCTOBER2018 www.ti.com
1.4 Functional Block Diagram
AVSS AVDD HPVSS HPVDD SPLVSS SPRVSS SPLVDD SPRVDD
P0/R116
7-Bit
VOL/MICDET Vol
ADC
Left and Right Audio Output Stage
Volume-Control Register Power Management
P0/R117
P1/R33–R34
GPIO1 GPIO
De-Pop
SDA I2C and
SCL Soft Start
RC CLK
AIN1
AIN2
Analog Class-D Speaker
Note: Normally, Attenuation Driver
MCLK is PLLinput; 0 dB to–78 dB
however, BCLK or and Mute 6 dB to 24 dB
GPIO1 can also be P0/R63/D5–D4 (0.5-dB steps) (6-dB steps)
PLLinput.
LData Left DAC AIN1 P1/R38 P1/R42
R Data S SPLP
MCLK PLL (L+R)/2 Data DAC SPLM
Analog ClassA/B
Attenuation Headphone/Lineout
0 dB to–78 dB Driver
WCLK and Mute 0 dB to 9 dB
SDIN (0.5-dB steps) (1-dB steps)
BCLK Serial P1/R36 P1/R40
Interface Proincegss- D2i4g itdaBl Vtool AIN2 HPL
and Blocks Mute MIXER P1/R30–R31
RESET Clocks P1/R35
Analog Class-D Speaker
Attenuation Driver
0 dB to–78 dB
and Mute 6 dB to 24 dB
P0/R63/D3–D2 (0.5-dB steps) (6-dB steps)
Right DAC P1/R39 P1/R43
LData
R Data S SPRP
DAC
(L+R)/2 Data SPRM
P0/R64–R66 Analog ClassA/B
Attenuation Headphone/Lineout
0 dB to–78 dB Driver
and Mute 0 dB to 9 dB
P1/R46 2 V/2.5 V/AVDD (0.5-dB steps) (1-dB steps)
MICBIAS P1/R37 P1/R41
HPR
P1/R30–R31
IOVSS IOVDD DVSS DVDD
B0360-02
Figure1-1.Functional BlockDiagram
NOTE
Thisdata manualis designedusingPDFdocument-viewingfeatures thatallowquick access
to information. Forexample,performingaglobalsearch onpage 0/register 27produces all
references to this page and register in a list. This makes it easy to traverse the list and find
all information related to a page and register. Note that the search string must be of the
indicated format. Also, this document includes document hyperlinks to allow the user to
quickly find a document reference. To come back to the original page, click the green left
arrownearthePDFpagenumberatthebottomofthefile.Thehot-keyforthisfunctionisalt-
left arrow on the keyboard. A different way to find information quickly is to use the PDF
bookmarks.
2 Introduction Copyright©2010–2018,TexasInstrumentsIncorporated
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2 Revision History
NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion.
ChangesfromRevisionA(May2012)toRevisionB Page
• AddedDeviceInformationtable,ESDRatingstable,FeatureDescriptionsection,Applicationand
Implementationsection,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentation
Supportsection,andMechanical,Packaging,andOrderableInformationsection. ......................................... 1
• AddedPower-SupplySequencesectiontotheDeviceInitializationsection................................................ 19
• ChangedSection6.3.10.1.2diagramsforPRB_P2/5/8/10/13/15/18/21/24/25toreflectthattheDRC_HPFfilter
cannotbebypassedwhentheDRCisturnedoff .............................................................................. 26
• Addedsequenceforinsertingabeepinthemiddleofanalready-playingsignalandnotetextfollowingscriptin
theKey-ClickFunctionalityWithDigitalSine-WaveGenerator(PRB_P25)section........................................ 42
• ChangedPRB_RxtoPRB_PxinDACSetupsection.......................................................................... 48
• Changedtextfrom:"therisingedgeofthewordclock..."To:"therisingedgeofthewordclock..."intheDSPMode 60
• ChangedDOSRnoteinPage0/Register14byswitchingmultiplevalueforFilterTypeAandFilterTypeC........ 68
• ChangeddescriptioninPage0/Register14toremoveparametersforminiDSP......................................... 68
• Changedresetvaluetoincludeallbitsinsteadofjusttwo(xx)............................................................... 74
• DeletedreferencetoDig_Mic_IninPage0/Register54tableforbitsD2-D1............................................. 75
• ChangedvaluesinPage0/Register69(0x45):DRCControl2............................................................. 78
• ChangedPage0,Register70,bitD3-D0decayratevaluefor0000fromDR=1.5625e–3toDR=0.015625........ 78
• SwitchedD1andD0descriptionssothatD1isforSPandD0isforHPinPage1/Register30table................ 81
• ChangedPage1/Register40,D1toreserved................................................................................. 84
• ChangedPage1/Register41,D1toreserved................................................................................. 84
• AddedFigure9-1 ................................................................................................................. 100
ChangesfromOriginal(January,2010)toRevisionA Page
• Changedregister36toregister35................................................................................................ 24
• AddedD6–D0totheRegisterValuecolumnheadingandchangedAnalogAttenuationtoAnalogGain............... 45
• DeletedAnalogVolumeControlforHeadphoneandSpeakerOutputs(forD7=0)tableandaddedtablenoteto
D7=1table............................................................................................................................ 45
• Changedpage0topage1insection5.5.12.1.................................................................................. 46
• Added80MHz≤(PLL_CLKIN×J.D×R/P)≤110MHzand4≤R×J≤259underneathEquation8.................. 55
• AddedTimersectionandimageafterPLLsection.............................................................................. 57
• AddedtablenotetoPage0/Register64(0x40):DACVOLUMECONTROL.............................................. 76
• ChangedD0=1toReservedinPage1/Register33........................................................................... 82
• Removedextraneouscross-referencesfordeletedtable...................................................................... 83
• AddedtablenotefollowingPage1/Register40............................................................................... 84
• AddedtablenotetoPage1/Register41(0x29):HPRDriver................................................................ 84
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3 Pin Configuration and Functions
RHB Package
(Top View)
D D S
VD M P VD VS M S D
R R L L L L S D
P P P P P P V V
S S S S S S D A
24 23 22 21 20 19 18 17
SPRVSS 25 16 AVSS
SPRP 26 15 NC
HPL 27 14 AIN2
HPVDD 28 13 AIN1
HPVSS 29 12 MICBIAS
HPR 30 11 VOL/MICDET
RESET 31 10 SCL
GPIO1 32 9 SDA
1 2 3 4 5 6 7 8
S D D C N K K K
VS VD VD N DI CL CL CL
O O D W B M
I I
P0048-14
3.1 Pin Attributes
Table3-1.PinFunctions
PIN
I/O DESCRIPTION
NAME NO.
AIN1 13 I Analoginput#1routedtooutputmixer
AIN2 14 I Analoginput#2routedtooutputmixer
AVDD 17 – Analogpowersupply
AVSS 16 – Analogground
BCLK 7 I/O Audioserialbitclock
DIN 5 I Audioserialdatainput
DVDD 3 – Digitalpower–digitalcore
DVSS 18 – Digitalground
GPIO1 32 I/O General-purposeinput/outputandmultifunctionpin
HPL 27 O Left-channelheadphone/linedriveroutput
HPR 30 O Right-channelheadphone/linedriveroutput
HPVDD 28 – Headphone/linedriverandPLLpower
HPVSS 29 – Headphone/linedriverandPLLground
IOVDD 2 – Interfacepower
IOVSS 1 – Interfaceground
MCLK 8 I Externalmasterclock
MICBIAS 12 – Microphonebiasforexternalmicrophone
NC 4,15 I Noconnecton
RESET 31 I Devicereset
SDL 10 I/O I2Ccontrolbusclockinput
SDA 9 I/O I2Ccontrolbusdatainput
SPLM 19 O Left-channelclass-Dspeaker-driverinvertingoutput
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Table3-1. PinFunctions (continued)
PIN
I/O DESCRIPTION
NAME NO.
SPLP 22 O Left-channelclass-Dspeaker-drivernoninvertingoutput
SPLVDD 21 – Left-channelclass-Dspeaker-driverpowersupply
SPLVSS 20 – Left-channelclass-Dspeaker-driverpowersupplyground
SPRM 23 O Right-channelclass-Dspeaker-driverinvertingoutput
SPRP 26 O Right-channelclass-Dspeaker-drivernoninvertingoutput
SPRVDD 24 – Right-channelclass-Dspeaker-driverpowersupply
SPRVSS 25 – Right-channelclass-Dspeaker-driverpower-supplyground
Volumecontrolorheadphonedetection.Notethatmicrophonedetectionisalsoavailableon
VOL/MICDET 11 I
devicesthathaveanADC.
WCLK 6 I/O Audioserialwordclock
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Table of Contents
1 Introduction............................................... 1 4.9 DSPTiminginSlaveMode......................... 12
1.1 Features.............................................. 1 4.10 I2CInterfaceTiming................................. 13
........................................... ..............................
1.2 Applications 1 4.11 TypicalCharacteristics 14
1.3 Description............................................ 1 5 ParameterMeasurementInformation.............. 17
1.4 FunctionalBlockDiagram............................ 2 6 DetailedDescription................................... 18
2 Revision History......................................... 3 6.1 Overview............................................ 18
3 PinConfigurationandFunctions..................... 4 6.2 FunctionalBlockDiagram........................... 19
......................................... .................................
3.1 PinAttributes 4 6.3 FeatureDescription 19
4 Specifications ............................................ 7 6.4 RegisterMap........................................ 65
4.1 AbsoluteMaximumRatings.......................... 7 7 ApplicationandImplementation.................... 97
.......................................... ..............................
4.2 ESDRatings 7 7.1 ApplicationInformation 97
................ ..................................
4.3 RecommendedOperatingConditions 7 7.2 TypicalApplication 97
4.4 Thermal Information.................................. 8 8 PowerSupplyRecommendations.................. 99
4.5 ElectricalCharacteristics............................. 8 9 Layout................................................... 100
........................... ..................................
4.6 PowerDissipationRatings 9 9.1 Layout Guidelines 100
4.7 I2S,LJF,andRJFTiminginSlaveMode........... 10 9.2 LayoutExample.................................... 100
........................
4.8 DSPTiminginMasterMode 11
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4 Specifications
4.1 Absolute Maximum Ratings
overoperatingfree-airtemperaturerange(unlessotherwisenoted) (1)
MIN MAX UNIT
AVDDtoAVSS -0.3 3.9 V
DVDDtoDVSS -0.3 2.5 V
HPVDDtoHPVSS -0.3 3.9 V
SPLVDDtoSPLVSS -0.3 6 V
SPRVDDtoSPRVSS -0.3 6 V
IOVDDtoIOVSS -0.3 3.9 V
Digitalinputvoltage IVOSS–0.3 IVODD+0.3 V
Analoginputvoltage AVSS–0.3 AVDD+0.3 V
Operatingtemperature –40 85 °C
Junctiontemperature(TJMax) 105 °C
Storagetemperature,T -55 150 °C
stg
Powerdissipation (T Max-T )/R W
J A θJA
R thermalimpedance(withthermalpadsolderedtoboard) 35 °C/W
θJA
(1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings
only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating
Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
4.2 ESD Ratings
VALUE UNIT
Electrostatic Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000
V V
(ESD) discharge Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±1000
(1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess.
(2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess.
4.3 Recommended Operating Conditions
overoperatingfree-airtemperaturerange(unlessotherwisenoted)
MIN NOM MAX UNIT
AVDD(1) ReferencedtoAVSS(2) 2.7 3.3 3.6
DVDD ReferencedtoDVSS (2) 1.65 1.8 1.95
HPVDD ReferencedtoHPVSS(2) 2.7 3.3 3.6
Power-supplyvoltage V
SPLVDD(1) ReferencedtoSPLVSS(2) 2.7 5.5
SPRVDD(1) ReferencedtoSPRVSS(2) 2.7 5.5
IOVDD ReferencedtoIOVSS(2) 1.1 3.3 3.6
Resistanceappliedacrossclass-D
Speakerimpedance 8 Ω
outputpins(BTL)
Headphoneimpedance ACcoupledtoR 16 Ω
L
V Analogaudiofull-scaleinputvoltage AVDD=3.3V,single-ended 0.707 V
I RMS
Stereolineoutputloadimpedance ACcoupledtoR 10 kΩ
L
MCLK(3) Masterclockfrequency IOVDD=3.3V 50 MHz
f SCLclockfrequency 400 kHz
SCL
T Operatingfree-airtemperature –40 105 °C
A
(1) Tominimizebattery-currentleakage,theSPLVDDandSPRVDDvoltagelevelsmustnotbebelowtheAVDDvoltagelevel.
(2) Allgroundsonboardaretiedtogether,sotheymustnotdifferinvoltagebymorethan0.2-Vmaximumforanycombinationofground
signals.Byuseofawidetraceorgroundplane,ensurealow-impedanceconnectionbetweenHPVSSandDVSS.
(3) Themaximuminputfrequencymustbe50MHzforanydigitalpinusedasageneral-purposeclock.
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4.4 Thermal Information
TLV320DAC3101
THERMALMETRIC(1) RHB(VQFN) UNIT
32PINS
R Junction-to-ambientthermalresistance 32.7 °C/W
θJA
R Junction-to-case(top)thermalresistance 23.2 °C/W
θJC(top)
R Junction-to-boardthermalresistance 6.6 °C/W
θJB
ψ Junction-to-topcharacterizationparameter 0.3 °C/W
JT
ψ Junction-to-boardcharacterizationparameter 6.5 °C/W
JB
R Junction-to-case(bottom)thermalresistance 2 °C/W
θJC(bot)
(1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication
report.
4.5 Electrical Characteristics
At25°C,AVDD=HPVDD=IOVDD=3.3V,SPLVDD,SPRVDD=3.6V,DVDD=1.8V,f (audio)=48kHz,CODEC_CLKIN
S
=256×f ,PLL=Off,VOL/MICDETpindisabled(unlessotherwisenoted)
S
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
INTERNALOSCILLATOR—RC_CLK
Oscillatorfrequency 8.2 MHz
VOLUMECONTROLPIN(ADC);VOL/MICDETpinenabled
VOL/MICDETpinconfiguredasvolumecontrol(page0/register116,bitD7=1and 0.5x
Inputvoltagerange 0 V
page0/register67,bitD7=0) AVDD
Inputcapacitance 2 pF
Volumecontrolsteps 128 Steps
MICROPHONEBIAS
Page1/register46,bitsD1–D0=10 2.25 2.5 2.75
Voltageoutput V
Page1/register46,bitsD1–D0=01 2
At4-mAloadcurrent,page1/register46,bitsD1–D0=10(MICBIAS=2.5V) 5
Voltageregulation mV
At4-mAloadcurrent,page1/register46,bitsD1–D0=01(MICBIAS=2V) 7
DACHEADPHONEOUTPUT,AC-coupledload=16Ω(single-ended),drivergain=0dB,parasiticcapacitance=30pF
Full-scaleoutputvoltage(0dB) Outputcommon-modesetting=1.65V 0.707 VRMS
SNR Signal-to-noiseratio Measuredasidle-channelnoise,A-weighted(1)(2) 80 95 dB
THD Totalharmonicdistortion 0-dBFSinput –85 –65 dB
THD+N Totalharmonicdistortion+noise 0-dBFSinput –82 –60 dB
Muteattenuation 87 dB
PSRR Power-supplyrejectionratio(3) RippleonHPVDD(3.3V)=200mVp-pat1kHz –62 dB
PO Maximumoutputpower RRLL==3126ΩΩ,,TTHHDD++NN==––6600ddBB 2600 mW
(1) Ratioofoutputlevelwith1-kHzfull-scalesine-waveinput,totheoutputlevelwiththeinputsshort-circuited,measuredA-weightedovera
20-Hzto20-kHzbandwidthusinganaudioanalyzer.
(2) Allperformancemeasurementsdonewith20-kHzlow-passfilterand,wherenoted,A-weightedfilter.Failuretousesuchafiltermay
resultinhigherTHD+NandlowerSNRanddynamicrangereadingsthanshownintheElectricalCharacteristics.Thelow-passfilter
removesout-of-bandnoise,which,althoughnotaudible,mayaffectdynamicspecificationvalues.
(3) DACtoheadphone-outPSRRmeasurementiscalculatedasPSRR=20×log(ΔV /ΔV ).
HPL HPVDD
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Electrical Characteristics (continued)
At25°C,AVDD=HPVDD=IOVDD=3.3V,SPLVDD,SPRVDD=3.6V,DVDD=1.8V,f (audio)=48kHz,CODEC_CLKIN
S
=256×f ,PLL=Off,VOL/MICDETpindisabled(unlessotherwisenoted)
S
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
DACLINEOUT(HPDriverinLineoutMode)
SNR Signal-to-noiseratio Measuredasidle-channelnoise,A-weighted 95 dB
THD Totalharmonicdistortion 0-dBFSinput,0-dBgain –86 dB
THD+N Totalharmonicdistortion+noise 0-dBFSinput,0-dBgain –82 dB
DACDigitalInterpolationFilterCharacteristics
SeeSection6.3.10.1.4forDACinterpolationfiltercharacteristics.
DACOutputtoClass-DSpeakerOutput;Load=8Ω(Differential),50pF
SPLVDD=SPRVDD=3.6V,BTLmeasurement,CM=1.8V,DACinput=0dBFS,
2.2
class-Dgain=6dB,THD=–16.5dB
Outputvoltage SPLVDD=SPRVDD=3.6V,BTLmeasurement,CM=1.8V,DACinput=–2dBFS, VRMS
2.1
class-Dgain=6dB,THD=–20dB
SPLVDD=SPRVDD=3.6V,BTLmeasurement,DACinput=mute,CM=1.8V,
Output,common-mode 1.8 V
class-Dgain=6dB
SPLVDD=SPRVDD=3.6V,BTLmeasurement,class-Dgain=6dB,measuredas
SNR Signal-to-noiseratio idle-channelnoise,A-weighted(withrespecttofull-scaleoutputvalueof2.2VRMS)(1) 87 dB
(2)
THD Totalharmonicdistortion SPLVDD=SPRVDD=3.6V,BTLmeasurement,CM=1.8V,class-Dgain=6dB –67 dB
THD+N Totalharmonicdistortion+noise SPLVDD=SPRVDD=3.6V,BTLmeasurement,CM=1.8V,class-Dgain=6dB –66 dB
PSRR Power-supplyrejectionratio(4) SPLVDD=SPRVDD=3.6V,BTLmeasurement,rippleonSPLVDD/SPRVDD=200 –44 dB
mVp-pat1kHz
Muteattenuation 110 dB
SPLVDD=SPRVDD=3.6V,BTLmeasurement,CM=1.8V,class-Dgain=18dB,
540 mW
THD=10%
SPLVDD=SPRVDD=4.3V,BTLmeasurement,CM=1.8V,class-Dgain=18dB,
PO Maximumoutputpower THD=10% 790 mW
SPLVDD=SPRVDD=5.5V,BTLmeasurement,CM=1.8V,class-Dgain=18dB,
1.29 W
THD=10%
Output-stageleakagecurrent
SPLVDD=SPRVDD=4.3V,device
SPLVDD=SPRVDD=4.3V,deviceispowereddown(power-up-resetcondition) 80 nA
ispoweredfordirectbattery
connection
DACPowerConsumption
ForDACpowerconsumptionbasedontheselectedprocessingblock,seeSection6.3.8.
DIGITALINPUT/OUTPUT
Logicfamily CMOS
0.7×
VIH IIH=5µA,IOVDD≥1.6V IOVDD
IIH=5µA,IOVDD<1.6V IOVDD
0.3×
VIL LogicLevel IIL=5µA,IOVDD≥1.6V –0.3 IOVDD V
IIL=5µA,IOVDD<1.6V 0
0.8×
VOH IOH=2TTLloads IOVDD
0.1×
VOL IOL=2TTLloads IOVDD
Capacitiveload 10 pF
(4) DACtospeaker-outPSRRmeasurementiscalculatedasPSRR=20×log(ΔV /ΔV ).
SPL(P+M) SPLVDD
4.6 Power Dissipation Ratings
Thisdatawastakenusing2-oz.(0,071-mmthick)traceandcopperpadthatissolderedtoaJEDEChigh-K,standard4-layer
3-inch×3-inch(7,62-cm×7,62-cm)PCB.
PowerRatingat25°C DeratingFactor PowerRatingat70°C PowerRatingat85°C
2.3W 28.57mW/°C 1W 0.6W
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4.7 I2S, LJF, and RJF Timing in Slave Mode
Allspecificationsat25°C,DVDD=1.8V
Note:Alltimingspecificationsaremeasuredatcharacterization.
WCLK
t (WS) t
h r
t (BCLK) t (WS)
H S
BCLK
t (BCLK)
L
t (DI) t
S f
DIN
t (DI)
h
T0145-11
IOVDD=1.1V IOVDD=3.3V
PARAMETER UNIT
MIN MAX MIN MAX
t (BCLK) BCLKhighperiod 35 35 ns
H
t (BCLK) BCLKlowperiod 35 35 ns
L
t(WS) WCLKsetup 8 6 ns
s
t (WS) WCLKhold 8 6 ns
h
t(DI) DINsetup 8 6 ns
s
t (DI) DINhold 8 6 ns
h
t Risetime 4 4 ns
r
t Falltime 4 4 ns
f
Figure4-1.I2S,LJF,andRJFTiminginSlaveMode
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