Low power high speed and high accuracy design methodologies for pipeline Analog-to-Digital

154 Pages·2017·2.42 MB·English

by  Vipul Katyal

Iowa State University Capstones, Theses and
Retrospective Theses and Dissertations
Dissertations
2008
Low power high speed and high accuracy design
methodologies for pipeline Analog-to-Digital
converters
Vipul Katyal
Iowa State University
Follow this and additional works at:https://lib.dr.iastate.edu/rtd
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Recommended Citation
Katyal, Vipul, "Low power high speed and high accuracy design methodologies for pipeline Analog-to-Digital converters" (2008).
Retrospective Theses and Dissertations. 15706.
https://lib.dr.iastate.edu/rtd/15706
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Low power high speed and high accuracy design methodologies for Pipeline Analog-to-
Digital converters

by

Vipul Katyal

A dissertation submitted to the graduate faculty

in partial fulfillment of the requirements for the degree of

DOCTOR OF PHILOSOPHY

Major: Electrical Engineering

Program of Study Committee:
Randall L. Geiger, Co-major Professor
Degang J. Chen, Co-major Professor
Chirs Chong-Nuen Chu
Ratnesh Kumar
Richard J. Martin

Iowa State University

Ames, Iowa

2008

Copyright © Vipul Katyal, 2008. All rights reserved.
3316231

3316231
2008
ii
DEDICATION

I would like to dedicate this thesis to my father, Dr. O. P. Katyal, an inspiring teacher of
physics, to my mother, Ms. M. Katyal, and to my wife, Ms. J. Agashe, for their motivation,
support and guidance without which I would not have been able to complete this work.
iii
TABLE OF CONTENTS
LIST OF FIGURES..................................................................................................................v
LIST OF TABLES..................................................................................................................vii
ABSTRACT...........................................................................................................................viii
CHAPTER 1. GENERAL OVERVIEW..................................................................................1
References.................................................................................................................8
CHAPTER 2. POWER DEPENDENCE OF FEEDBACK AMPLIFIERS ON OPAMP
ARCHITECTURE..................................................................................................................11
Abstract...................................................................................................................11
2.1 Introduction......................................................................................................11
2.2 Amplifier Optimization Formulation...............................................................13
2.2.1 Single Stage Amplifier (Case 1)...............................................................14
2.2.2 Two Stage Miller Compensated Amplifier (Case 2)................................21
2.2.2.1 Poles and Zero Consideration............................................................23
2.2.2.2 Parasitic Consideration......................................................................24
2.2.2.3 Gain Enhancement Techniques.........................................................29
2.2.2.4 Power Reduction Technique..............................................................29
2.2.3 Two Stage Miller and Resistive Compensated Amplifier (Case 3)..........30
2.3 Results..............................................................................................................35
2.4 Conclusion.......................................................................................................37
2.5 Acknowledgement...........................................................................................37
References...............................................................................................................37
CHAPTER 3. A NEW HIGH PRECISION LOW OFFSET DYNAMIC COMPARATOR
FOR HIGH RESOLUTION HIGH SPEED ADCS................................................................40
Abstract...................................................................................................................40
3.1 Introduction......................................................................................................41
3.2 Dynamic Comparator Design..........................................................................45
3.2.1 Differential Pair Comparator....................................................................45
3.2.2 Proposed Comparator................................................................................48
3.3 Sensitivity analysis..........................................................................................50
3.4 Simulation Results...........................................................................................52
3.5 Conclusions......................................................................................................64
3.6 Acknowledgement...........................................................................................64
References...............................................................................................................64
CHAPTER 4. KT/C CONSTRAINT OPTIMIZATION OF POWER IN PIPELINE ADCS 67
Abstract...................................................................................................................67
4.1 Introduction......................................................................................................67
4.2 Power Optimization.........................................................................................69
4.2.1 Power Consumption Sources....................................................................69
4.2.2 Power Analysis of Pipeline Stages...........................................................71
4.3 Results..............................................................................................................76
4.4 Conclusions......................................................................................................79
iv
References...............................................................................................................79
CHAPTER 5. STAITISCAL MODELING OF OVER-RANGE PROTECTION
REQUIREMENT FOR A SWITCHED CAPACITOR INTER-STAGE GAIN AMPLIFIER
.................................................................................................................................................81
Abstract...................................................................................................................81
5.1 Introduction......................................................................................................82
5.2 Output Voltage Variation.................................................................................84
5.2.1 Charge-Redistribution Switched Capacitor Amplifier (CR-SC Amp).....85
5.2.2 Flip-Around Switched Capacitor Amplifier (FA-SC Amp).....................89
5.3 Results..............................................................................................................91
5.4 Conclusion.......................................................................................................96
5.5 Acknowledgement...........................................................................................97
References...............................................................................................................97
CHAPTER 6. NEW OVER-RANGE PROTECTION SCHEME IN PIPELINE DATA
CONVERTERS....................................................................................................................101
Abstract.................................................................................................................101
6.1 Introduction....................................................................................................102
6.2 Linearity and Over-ranging...........................................................................103
6.2.1 Operating Windows................................................................................103
6.2.2 Critical Points..........................................................................................107
6.3 Strategies for Providing Over-Range Protection...........................................108
6.3.1 Critical Window......................................................................................109
6.4 Conlusions.....................................................................................................112
References.............................................................................................................112
CHAPTER 7. ADJUSTABLE HYSTERESIS CMOS SCHMITT TRIGGERS..................114
Abstract.................................................................................................................114
7.1 Introduction....................................................................................................114
7.2 Traditional Inverter based Schmitt triggers...................................................116
7.3 New Schmitt Trigger Design.........................................................................119
7.4 Simulation Results.........................................................................................122
7.5 Conclusions....................................................................................................132
References.............................................................................................................132
CHAPTER 8. GENERAL CONCLUSIONS AND FUTURE WORK................................134
8.1 General Conclusions......................................................................................134
8.2 Recommendations for Future Research.........................................................137
APPENDIX Settling Time and Gain-Bandwidth Relationship...........................................139
ACKNOWLEDGEMENTS..................................................................................................143
v
LIST OF FIGURES
Figure 1.1 Basic Pipeline ADC Architecture...........................................................................2
Figure 1.2 kth Stage of a Pipeline ADC...................................................................................3
Figure 2.1 Negative Feedback Configuration........................................................................13
Figure 2.2 Single Stage Amplifier.........................................................................................14
Figure 2.3 Transistor Layout..................................................................................................16
Figure 2.4 Single Stage Amplifier Gain-Bandwidth Product vs. Power...............................17
Figure 2.5 Power vs. V for Single Stage Amplifier...........................................................19
EB1
Figure 2.6 Two Stage Miller Compensated Amplifier..........................................................21
z
Figure 2.7 as a function of β and θ................................................................................25
p
2
Figure 2.8 GB vs. Power for a Two Stage Miller Compensated Amplifier...........................26
Figure 2.9 θP vs. γV for Two Stage Miller compensated Amplifier................................28
EB1
Figure 2.10 Two Stage Miller and Resistive Compensated Amplifier..................................31
Figure 2.11 GB vs. Power for a Two Stage Miller and Resistive Compensated Amplifier..34
Figure 2.12 θP vs. γV for Two Stage Miller and Resistive Compensated Amplifier.......34
EB1
Figure 2.13 β vs. GB (a) Q = 1/3 (or η = 1/9) (b) Q = 1/2 (or η = 1/4)...........................36
crit
Figure 3.1 Resistor Divider (or Lewis-Gray) Dynamic Comparator.....................................42
Figure 3.2 Differential Pair Dynamic Comparator................................................................43
Figure 3.3 Capacitive Differential Pair Dynamic Comparator..............................................43
Figure 3.4 Output node during enable high (a) discharging phase and (b) charging phase..46
Figure 3.5 Typical time domain transition curve of a dynamic comparator..........................47
Figure 3.6 Proposed Dynamic Comparator...........................................................................48
Figure 3.7 Restricted Signal Swing Clock Generator (a) Method 1 (b) Method 2................49
Figure 3.8 Dynamic Comparator Offset Definition...............................................................51
Figure 3.9 Offset definition in presence of hysteresis in a dynamic comparator..................52
Figure 4.1 Basic Pipeline Data Converter Architecture.........................................................69
Figure 4.2 kth Stage of Basic Pipeline Data Converter..........................................................70
Figure 4.3 kth Stage MDAC (Flip-Around Switched Cap. Amp.) of a Pipeline ADC..........72
Figure 4.4 kth Stage Operational Amplifier during Phase φ .................................................73
2
Figure 5.1 Errors in a Single Transfer Curve (a) Amplifier Offset or Sub-DAC Errors (b)
Stage Gain Errors (c) Comparator Offset Errors............................................................82
Figure 5.2 Pipeline ADC Single Stage Residue Transfer......................................................84
Figure 5.3 Charge-Redistribution Switched Capacitor Amplifier (MDAC).........................85
Figure 5.4 Modified Charge-Redistribution Switched Capacitor Amplifier (MDAC)..........88
Figure 5.5 Flip-Around Switched Capacitor Amplifier (MDAC).........................................89
Figure 5.6 Modified Flip-Around Switched Capacitor Amplifier (MDAC).........................90
Figure 5.7 Single Stage Pipeline ADC Transfer Curve.........................................................91
Figure 5.8 3σ vs. σ for a CR-SC Amplifier (a) σ = 0.01 (b) σ = 0.1.............92
V Amp C C
OUT,TP OS
Figure 5.9 3σ vs. σ for a CR-SC Amplifier with σ = 10mV.......................93
V Comp Amp
OUT,TP OS OS
Figure 5.10 3σ vs. σ for a FA-SC Amplifier........................................................94
V C
OUT,TP,Worst
vi
Figure 5.11 3σ vs. σ for a FA-SC Amp. (a) σ = 0.01 (b) σ = 0.1............95
V Comp C C
OUT,TP,Worst OS
Figure 6.1 Block Diagram of kth stage of a pipeline ADC..................................................103
Figure 6.2 Input and Output ranges of Amplifier Stage in Pipeline ADC...........................104
Figure 6.3 Effects of Driving Residue Amplifier Beyond the DCRW................................106
Figure 6.4 Critical Points (CPs) for One-Bit per Stage Pipeline ADC................................108
Figure 6.5 1-Bit/Stage Structure Showing Over-Range Sensitive Regions in Red Circles.109
Figure 6.6 Different Possible Critical Windows (CWs) and New Critical Window (NCW)
.......................................................................................................................................110
Figure 6.7 Flow Chart for New Over-Range Protection Scheme........................................111
Figure 7.1 Traditional inverter based Schmitt Trigger (Str. 1)............................................117
Figure 7.2 Hysteresis curve for V vs V ........................................................................118
INT IN
Figure 7.3 Proposed Schmitt Trigger design (Str. 2)...........................................................119
Figure 7.4 Modified Proposed Schmitt Trigger design (Str. 3)...........................................120
Figure 7.5 Two input inverter for NMOS (INV ).......................................................121
FB 2NFB
Figure 7.6 Two input inverter for PMOS (INV )........................................................121
FB 2PFB
Figure 7.7 Tip Point Variations vs. Feedback Inverter’s (INV ) (W , W ) for Str. 1.....129
OUT N P
Figure 7.8 Trip Point Variations vs. Feedback Inverter’s (INV ) (W , W ) for Str. 2....130
NFB N P
Figure 7.9 Trip Point Variations vs. Feedback Inverter’s (INV ) (W , W ) for Str. 2....130
PFB N P
Figure 7.10 Trip Point Variations vs. Feedback Inv.’s (INV ) (W , W , W ) for Str. 3
2NFB N1 N2 P
.......................................................................................................................................131
Figure 7.11 Trip Point Variations vs. Feedback Inv.’s (INV ) (W , W , W ) for Str. 3
2PFB N P1 P2
.......................................................................................................................................131
vii
LIST OF TABLES
Table 2.1 Comparison of Power Requirements for the Three Structures..............................35
Table 3.1 Key Values Used for Simulations for Dynamic Comparator Characterization.....53
Table 3.2 Comparator Offset Due to Additional Parasitic (C ) at V− ..................................54
P out
Table 3.3 Comp. Offset Due to Additional Parasitic (C ) at V− with D & D Reset.........54
P out 1 2
Table 3.4 Comp. Offset Due to Additional Parasitic (C ) at D Node..................................56
P 1
Table 3.5 Comp. Offset Due to Additional Parasitic (C ) at D Node with D & D Reset..56
P 1 1 2
Table 3.6 Comp. Offset Due to Input Common Mode Voltage Errors..................................57
Table 3.7 Comp. Offset Due to Clock Timing Errors............................................................57
Table 3.8 Comp. Offset Due to Additional Parasitic (C ) at V− with 3x inverter load.......59
P out
Table 3.9 Comp. Offset Due to Additional Parasitic at V− with 3x inv. load & 100Hz clk.59
out
Table 3.10 Comp. Offset Due to Additional Parasitic at D Node with 3x inverter load......60
1
Table 3.11 Comp. Offset Due to Common Mode Voltage Errors with 3x inverter load.......61
Table 3.12 Comp. Offset Due to Clock Timing Errors with 3x inverter load.......................61
Table 3.13 Comp. Offset Due to Additional Parasitic of 1fF at V− with 3x inverter load for
out
different differential pair sizing......................................................................................63
Table 3.14 Comp. Offset Due to Additional Parasitic of 1fF at V− with 3x inverter load for
out
different comparator sizing.............................................................................................63
Table 4.1 Normalized Power and Capacitance Requirements of Pipeline ADC for Different
Capacitor Scaling and Effective Number of Bits per Stage............................................78
Table 5.1 Comparison Between CR-SC and FA-SC Structures Without Offset Cancellation
Techniques......................................................................................................................95
Table 5.2 Comparison Between CR-SC and FA-SC Structures with Offset Cancellation
Techniques......................................................................................................................96
Table 7.1 Key Values Used for Simulations for Schmitt Trigger Design...........................123
Table 7.2 Tip Point Variations vs. Feedback Inverter INV for Str. 1............................126
OUT
Table 7.3 Trip Point Variations vs. Feedback Inverter INV for Str. 2...........................126
NFB
Table 7.4 Trip Point Variations vs. Feedback Inverter INV for Str. 2............................127
PFB
Table 7.5 Trip Point Variations vs. Feedback Inverter INV for Str. 3..........................127
2NFB
Table 7.6 Trip Point Variations vs. Feedback Inverter INV for Str. 3..........................128
2PFB
Table 7.7 Hysteresis Variation vs. Temperature..................................................................128
Table 7.8 Hysteresis Variation vs. Power Supply................................................................129
viii
ABSTRACT
Different aspects of power optimization of a high-speed, high-accuracy pipeline
Analog-to-Digital Converters (ADCs) are considered to satisfy the current and future needs
of portable communication devices. First power optimized design strategies for the amplifiers
are introduced. Closed form expressions of power w.r.t settling requirements are presented to
facilitate a fair comparison and selection of the amplifier structure. Next a new low offset
dynamic comparator has been designed. Simulation based sensitivity analysis is performed to
demonstrate the robustness of the new comparator with respect to stray capacitances,
common mode voltage errors and timing errors. With simplified amplifier power model
along with the use of dynamic comparators, a method to optimize the power consumption of
a pipeline ADC with kT/C noise constraint is also developed. The total power dependence on
capacitor scaling and stage resolution is investigated for a near-optimal solution.
After considering the power requirements of a pipeline ADC, design and statistical
modeling of over-range protection requirements is investigated. Closed form statistical
expressions for the over-range requirements are developed to assist in the allocation of the
error budgets to different pipeline blocks. A new over-range protection algorithm is also
developed that relaxes the amplifier design and power requirements.
Finally, two new CMOS Schmitt trigger designs are proposed which can be used as
clock inputs for the pipeline ADC. In the new designs, sizing of the feedback inverters is
used for independent trip point control. The new designs have also a modest reduction in
sensitivity to process variations along with immunity to the kick-back noise without the
addition of path delay.