Low-Power High-Speed ADCs for Nanometer CMOS Integration

102 Pages·2008·1.84 MB·English

by  Dr. Zhiheng Cao

Low-Power High-Speed ADCs
for Nanometer CMOS Integration
ANALOGCIRCUITSANDSIGNALPROCESSINGSERIES
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LOWPOWERUWBCMOSRADARSENSORS
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THEGM/IDDESIGNMETHODOLOGYFORCMOSANALOGLOWPOWERINTEGRATEDCIRCUITS
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CMOSCURRENT-MODECIRCUITSFORDATACOMMUNICATIONS
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Zhiheng Cao • Shouli Yan
Low-Power High-Speed
ADCs for Nanometer
CMOS Integration
ABC
Dr.ZhihengCao
Asst.Prof.ShouliYan
UniversityofTexas,Austin
CockrellSchoolofEngineering
Dept.Electrical&ComputerEngineering
1UniversityStation
AustinTX78712
ACESBldg.
USA
[email protected]
[email protected]
ISBN978-1-4020-8449-2 e-ISBN978-1-4020-8450-8
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Preface
Thisisabookaboutthedesignandimplementationdetailsofhigh-speedanalog-to-
digitalconverters(ADCs)inadvanceddigitalCMOSprocessesthatachievelower
power consumption for a given speed and resolution than conventional designs,
througharchitecturalandcircuitinnovationsthattakeadvantageofuniquefeatures
in nanometer CMOS processes. It includes a chapter for a phase lock loop (PLL)
clock multiplier which has also been designed using innovative circuit techniques
and successfully tested. It has been integrated for generating sampling clock to
oneADC.
Chapter1analyzestheobstaclesandopportunitiesinvolvedindevelopingADCs
and necessary clocking circuits in nanometer digital CMOS processes, such as
reduced transistor gain and linearity, increased switching speed, and increased
siliconarea.FivemostcommonlyusedADCarchitecturesarereviewed.Chapter2
describesa1.2V52mW210MS/s10-bitADCin130nmdigitalCMOSforappli-
cation to digital (low) IF receivers, whose advantage over the direct-conversion as
ahighlyintegratedreceiverarchitecturehasbeenshown[33,35].Usingaproposed
capacitornetworkimplementedwithsmallvalueinterconnectcapacitorswhichre-
places the power hungry resistor ladder in conventional sub-ranging ADCs, and
proposedoffsetcancelingcomparators,itachieves>70dBcSFDRupto100MHz
inputfrequencywhileconsumingonly52mW,whichisthelowestreportedtodate
for >200 MS/s 10-bit ADCs. The active area is 0.38 mm2 including decoupling
capswhichisalsocompetitivewithotherexisting10-bitpipelineADCs.Chapter3
presentsa1.2V32mW1.25GS/s6-bitADC(applicationsincludeseriallinks,disk
drives and UWB receivers) implemented in 130 nm digital CMOS [5]. This ADC
usesanewtypeofarchitecturethatcombinesflashandSARtoachievethelowest
powerconsumption,6-bit>1GS/sADCimplementationreportedinopenliterature
todate.TheSARinternalclockfrequencyis2.5GHz,whichisthefastesteverused
foraSARADC.Becauseitdoesnotrequireanycalibrationsteporpostprocessing,
andhasthesamelatencyasmostflashADC,itcanbeadirectdrop-inreplacement
of6-bitflashADCsinexistingapplicationtolowerpowerbymorethan5times[30].
Chapter4detailstheintegratedclock-multiplierPLLtogeneratesamplingandinter-
nalclockforthe1.25GS/sADC.Measurementshows0.4-ps-rmsjitter(integrated
v
vi Preface
from3kHzto300MHzoffset)for≥2.5GHzoutputsandtuningrangefrombelow
1 GHz up to 3 GHz. A new loop filter structure based on a sample-reset phase to
voltage converter and a Gm-C filter enables phase error preamplification to lower
PLLin-bandnoisewithoutincreasingloopfiltercapacitorsize.
ThisbookisbaseduponmyPh.D.dissertation;itincludesmoredetailsandmea-
surementresultsforeachproject,andacompletelynewchapterwhichdescribesthe
10-bit two-step ADC whose measurement finished only after I received my Ph.D.
degree,andisnotincludedinmydissertation.Becausethisbookfocusesonhigh-
speedADCs,itdoesnotincludeachapterforanearlyprojectofmyPh.D.research
—a14mW125MS/s1.25MHzsignalbandwidth84dBdynamicrange∆Σmod-
ulatorin0.25µmCMOS[4].
These projects I finished during my Ph.D. study in the University of Texas at
Austinwouldneverhavebeenpossiblewithoutthehelpandkindnessofmanyin-
dividuals. First of all, I would like to express my gratitude to my Ph.D. advisor,
ProfessorShouliYanforhisconfidenceinmeandenthusiasmfortheresultsofmy
work. He gave me countless insightful suggestions and guidance, and at the same
timealsoallowedmefreedomtopursuemyownideas.IamgratefultoMarcoCorsi
forgivingmetheopportunitytodoasix-monthinternatTexasInstrumentsin2007.
IsincerelythankBobPayneforhisguidanceduringmyintern.Thehighstandardin
robustnessofadesignwhichhekeepsanddemandswasveryinspirational.Iwased-
ucatedthatdesigningeventhesimplestcircuitisnotatrivialtask.Iwouldalsolike
to thank Yunchu Li, Richard Schreier, Steve Rose, Will Yang and other engineers
atAnalogDevicesfortheirguidanceanddiscussionsduringmyinternshipin2006.
Ilearnedmanyimportantprinciplesandfundamentalconceptsaboutanalog/mixed-
signaldesignthroughtakingMr.EricSwanson’scourseatUTinaveryearlystage
ofmystudy,towhichIamintenselygrateful.Ibenefitedalotfrommyfellowstu-
dents, especially Tongyu Song and Chaoming Zhang. Their attention to detail and
willingness to share information allowed me to spot several catastrophic mistakes
in my layout design which would certainly have lead to failure of the test chips.
TheirfriendshipmademystayatUTenjoyable.Theprojectsincludedinthisbook
wouldneverhavebeencompletedinatimelymannerwithoutthekindnessandhelp
ofKenAgeeandKennethHodsonatTexasInstrumentswhoallowedmetousethe
labstheymanage,andspenttheirtimehelpingmewiththetestsetupandsoldering
thetinychipontotheboardaftermyfailedattempts.Iappreciatethehelpfromthe
staffs in the computer engineering research center, especially Andrew Kieschnick
whoasoursystemadministratormaintainedaprimitivebutverycomfortableCAD
environment (Windows XP + VNC to Linux servers, Cadence custom flow with
UMCfoundrydesignkit+spectreRF+Calibre)withvirtuallynodowntimewhich
enabledefficientchipdevelopment(infact,fasterandlessstressfulthanmanypro-
prietaryCADsystemsIusedduringmyinternshipinindustry)andothercomputing
tasks.FinallyIwouldliketothankmyparentswhoencouragedandsupportedme
duringmystudy.
Contents
Preface............................................................ v
ListofTables ...................................................... ix
ListofFigures ..................................................... xi
1 Introduction................................................... 1
1.1 Motivations ............................................... 1
1.1.1 Analog-to-DigitalConverters .......................... 1
1.1.2 ClockGeneration .................................... 3
1.2 AReviewofExistingADCArchitectures ...................... 3
1.2.1 Flash .............................................. 3
1.2.2 Pipeline ............................................ 4
1.2.3 Subranging ......................................... 5
1.2.4 SuccessiveApproximation ............................ 6
1.2.5 ∆ΣADCs........................................... 8
2 A52mW10b210MS/sTwo-StepADCforDigitalIFReceivers
in130nmCMOS .............................................. 11
2.1 Background ............................................... 11
2.2 ArchitectureandCircuits .................................... 12
2.2.1 CapacitorSamplingNetwork/5b-DAC .................. 15
2.2.2 ConversionTimingDiagram........................... 17
2.2.3 SamplingClockSkewCalibration ...................... 18
2.2.4 6bFineADC ....................................... 20
2.2.5 OffsetCancelingComparator .......................... 25
2.2.6 5bCoarseADC ..................................... 25
2.3 ExperimentalResults ....................................... 27
2.3.1 TestSetup .......................................... 28
2.3.2 CharacterizationoftheClockDelayLine ................ 31
2.3.3 ADCMeasurementResults............................ 32
2.4 Summary ................................................. 39
vii
viii Contents
3 A32mW1.25GS/s6b2b/StepSARADCin130nm
DigitalCMOS ................................................. 41
3.1 Background ............................................... 41
3.2 Architecture ............................................... 42
3.3 EnablingCircuits........................................... 46
3.3.1 FastSettlingCapacitor-Network........................ 46
3.3.2 Flip-FlopBypassSARLogic .......................... 48
3.3.3 DigitalBackgroundOffsetCorrection ................... 50
3.3.4 High-SpeedLow-HysteresisComparator ................ 52
3.3.5 FloorPlanandLayoutConsiderations................... 55
3.4 TestingIssues.............................................. 57
3.4.1 CapturingADCOutputData........................... 57
3.4.2 SerialConfigurationInterface.......................... 59
3.4.3 TestSetup .......................................... 60
3.4.4 EvaluationBoardDesign.............................. 61
3.5 ExperimentalResults ....................................... 62
3.5.1 SummaryofResultsandDiscussions.................... 62
3.6 PerformanceSummaryandComparison ....................... 65
3.7 Summary ................................................. 66
4 A 0.4 ps-RMS-Jitter 1–3 GHz Clock Multiplier PLL
UsingPhase-NoisePreamplification .............................. 69
4.1 Introduction ............................................... 69
4.2 Phase-LockLoop(PLL)..................................... 71
4.2.1 Phase-to-VoltageConverterandLoopFilter .............. 71
4.2.2 PhaseErrorPreamplification........................... 74
4.2.3 ConstantLoop-BandwidthBiasing...................... 75
4.3 VCOandClockBuffers ..................................... 76
4.3.1 PhaseNoiseandPowerConsumptionProgrammability .... 76
4.3.2 VCOBufferwith50%DutyCycleOutput ............... 78
4.3.3 ReferenceClockReceiver ............................. 80
4.4 ExperimentalResults ....................................... 80
4.4.1 TestSetup .......................................... 80
4.4.2 MeasurementResultsandDiscussions................... 82
4.4.3 Comparison with Existing PLLs with Similar Output
FrequencyRange .................................... 83
4.5 Summary ................................................. 87
5 ConclusionsandFutureDirections............................... 89
References......................................................... 91
AbouttheAuthors.................................................. 95
List of Tables
2.1 Performancesummary ....................................... 38
2.2 Comparison with other recently published 10-bit CMOS
pipelineADCs.............................................. 38
3.1 Multiplexeroperation ........................................ 49
3.2 Performancesummary ....................................... 66
3.3 Comparisonwithotherpublished≥1GS/s6-bitCMOSADCs ..... 66
4.1 Comparison with other published PLLs with similar output
frequencyrange............................................. 87
ix
List of Figures
1.1 Intrinsicgain(a)andoutput-referredthirdorderintermodulation
interceptpoint(IP3)(b)vs.gate-overdrive voltageforvarious
CMOStechnologynodeswithL=1µm[1]...................... 2
1.2 BasicstructureofaflashADC................................. 4
1.3 Blockdiagramofatypical10-bitpipelinedADC................. 5
1.4 Basicstructureofatwo-stepsubrangingADC ................... 6
1.5 BasicstructureofaconventionalN-bitsuccessiveapproximation
ADC ...................................................... 7
1.6 Settling time-constant comparison between passive
switched-capacitor network and conventional OTA-based
switched-capacitorcircuits.................................... 8
1.7 Blockdiagramofasingle-bit∆ΣADC.......................... 9
2.1 Overallblockdiagramofthetwo-stepADC ..................... 13
2.2 Block diagram of the capacitor-sampling-network/5 b-DAC
andthe6bFADC ........................................... 14
2.3 Simplified schematic of the FADC sampling network
(fullydifferential,onesideshown) ............................. 16
2.4 Timingdiagramofthetwo-stepADC........................... 18
2.5 Clockskewcalibrationcircuits ................................ 19
2.6 Simulated clock edges of φ, φ and φ for fast, nominal
1 1P 1Q
andslowprocesscornerwithcodeatfull-scale................... 21
2.7 FADC’spreamplifiers........................................ 22
2.8 Simulated65inputwaveformstoeachstage-4preamp ............ 22
2.9 AschemeusedtoverifyifFADCpreampshavesufficientlinearity .. 24
2.10 Simplifiedschematicoftheproposedoffsetcancelingcomparator
usedbybothFADCandCADC................................ 26
2.11 Simplifiedschematicofthe5bCADC(fullydifferential,oneside
shown) .................................................... 27
2.12 Layoutofthetwo-stepADC .................................. 28
2.13 Diephotograph ............................................. 29
xi