Low-Power Design Techniques and CAD Tools for Analog and RF Integrated Circuits

329 Pages·2001·13.72 MB·English

by  Piet Wambacq

LOW-POWER DESIGN TECHNIQUES AND CAD TOOLS FOR ANALOG AND
RF INTEGRATED CIRCUITS
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Low-Power Design
Techniques and
CAD Tools for Analog and
RF Integrated Circuits
Edited by
Piet Wambacq
IMEC
Georges Gielen
Katholieke Universiteit Leuven
and
John Gerrits
CSEM System Engineering
Series Editors
Rene van Leuken
Alexander de Graaf
Reinder Nouta
TU Delft/DIMES, Delft, The Netherlands
KLUWER ACADEMIC PUBLISHERS
NEW YORK,BOSTON, DORDRECHT, LONDON, MOSCOW
eBookISBN: 0-306-48089-1
Print ISBN: 0-7923-7432-0
©2003 Kluwer Academic Publishers
NewYork, Boston, Dordrecht, London, Moscow
Print ©2001 Kluwer Academic Publishers
Dordrecht
All rights reserved
No part of this eBook maybe reproducedor transmitted inanyform or byanymeans,electronic,
mechanical, recording, or otherwise, without written consent from the Publisher
Created in the United States of America
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Contents
List of Figures xi
List of Tables xix
Contributing Authors xxi
Foreword xxv
Introduction xxxi
1
Motivation, context and objectives 1
Georges Gielen, Piet Wambacq, John F.M. Gerrits
2
Analysis and simulation of RF subsystems 9
Jaijeet Roychowdhury
2.1 Steady-state analysis 9
2.1.1 Harmonic Balance and Shooting 10
2.1.2 Fast Methods 12
2.2 Multitime analysis 14
2.2.1 Autonomous Systems: the Warped MPDE 18
2.2.2 Macromodelling time-varying systems 22
2.3 Noise in RF design 25
2.3.1 Mixing noise 27
2.3.2 Phase Noise 32
2.4 Conclusions 36
References 40
3
FAST: an efficient high-level dataflow simulator of mixed-signal front- 43
ends of digital telecom transceivers
Gerd Vandersteen, Piet Wambacq, Stéphane Donnay, Wolfgang Eberle Yves Rolain
v
vi LOW-POWER TECHNIQUES AND TOOLS FOR ANALOG AND RF IC’S
3.1 High-level models of front-end blocks 46
3.2 Multirate multicarrier (MRMC) representation of signals 47
3.3 Computation of the response to an MRMC signal 49
3.3.1 Combinatorial approach 49
3.3.2 Fourier transform approach 50
3.4 Construction of a computational graph 50
3.5 Scheduling and execution 51
3.6 Coupling of FAST with the digital simulation environment OCAPI 52
3.7 Runtime examples 53
3.7.1 Influence of the buffer size on the CPU time 53
3.7.2 Processing of nonlinear blocks 54
3.8 Conclusions 57
References 58
4
Efficient high-level simulation of analog telecom frontends 61
Piet Vanassche, Georges Gielen, Willy Sansen
4.1 Situating the exponential approach within a global framework for
simulation algorithms 62
4.1.1 Basic ideas behind simulation 63
4.1.2 An overview of some existing simulation algorithms 65
4.1.3 The complex damped exponential approach 67
4.2 The complex damped exponential basis and its signal modeling ca-
pabilities 67
4.3 A simulation approach using complex damped exponentials 70
4.3.1 Elementary arithmetics using exponentials 70
4.3.2 Algorithms for dealing with linear systems 70
4.3.3 Algorithms for dealing with weakly nonlinear systems 72
4.3.4 Conversion between sampled data and exponential represen-
tation 74
4.4 Experimental results 75
4.5 Conclusions 79
References 80
5
High-level power estimation of analog front-end blocks 83
Erik Lauwers, Georges Gielen
5.1 System design of telecom front ends 83
5.1.1 Localising the digital and the analog part 84
5.1.2 Refining the analog part 85
5.1.3 Conclusions from current system design and possible im-
provements 86
5.2 Analog power estimators 87
5.2.1 High-level power estimation 87
5.2.2 Construction of power estimators 89
5.2.2.1 First approach: bottom-up 89
Contents vii
5.2.2.2 Second approach: top-down 91
5.2.2.3 Illustration of both approaches 92
5.2.2.4 Conclusions 93
5.3 Examples of fundamental relations used to estimate the power con-
sumption 93
5.3.1 Analog integrated continuous-time filtering 93
5.3.2 Analog signal processing: mixers 94
5.3.3 Conclusions on fundamental estimators 95
5.4 Practical high-level power estimators 95
5.4.1 A power estimation model for high-speed CMOS ADCs 95
5.4.2 Power estimation using neural networks 98
5.4.3 High-level power estimation of analog continuous-time fil-
ters 99
5.4.4 Conclusion about practical estimators 103
5.5 Summary 103
References 104
6
Models and Analysis Techniques for Systematic Design and Verification 107
of Frequency Synthesizers
Bart De Smedt, Georges Gielen
6.1 Aspects of modeling 108
6.1.1 Why modeling ? 108
6.1.2 Modeling requirements 109
6.2 Introduction to frequency synthesizers 109
6.2.1 A typical frequency synthesizer topology 110
6.2.2 The design trade–off 111
6.3 Phase noise evaluation 112
6.3.1 Identification and quantification of noise sources 112
6.3.2 Propagation from the noise source to the output node 113
6.3.3 Combination of all contributions 114
6.3.4 Numerical aspects 115
6.4 Behavioral models for top–down design 116
6.4.1 Synthesizer models for transceiver functional–level design 118
6.4.2 Top–down behavioral–level models for synthesizer design 119
6.4.3 Illustration : settling time evaluation during top–downdesign 121
6.5 Behavioral models for bottom–up verification 122
6.5.1 Accuratenonlinear model of the local oscillator 123
6.5.2 Illustration : phase noise evaluation of a complete frequency
synthesizer at the verification stage 125
6.6 Summary 128
References 128
7
Nonlinear Symbolic Network Analysis: Algorithms and Applications to 131
RF Circuits
Wim Verhaegen, Georges Gielen
viii LOW-POWER TECHNIQUES AND TOOLS FOR ANALOG AND RF IC’S
7.1 Algorithm 132
7.1.1 Terminology 132
7.1.2 Description of the algorithm fundamentals 133
7.1.3 Nonlinearity stamps for 2nd– and 3rd–order analysis 137
7.2 Implementation of the algorithm 139
7.2.1 Error control algorithm 141
7.2.2 Error tolerances 142
7.3 Applications of nonlinear symbolic analysis 143
7.3.1 Two–stage miller–compensated opamp 143
7.3.2 Downconverting mixer 149
7.4 Conclusions 151
References 151
8
Approaches to Formal Verification of Analog Circuits 155
Lars Hedrich, Walter Hartong
8.1 Formal Verification: The Alternative Approach 155
8.1.1 Design Flow 156
8.1.2 Circuit Description 157
8.1.2.1 Circuit Classes 158
8.1.2.2 Other Approaches 159
8.2 Linear Dynamic Systems 160
8.2.1 Linear Circuit Description 160
8.2.2 Basic Algorithm 160
8.2.3 OuterEnclosure 160
8.2.4 Inner Enclosure 162
8.2.4.1 Safe Path Between Two Points 162
8.2.4.2 Inner Enclosure of a Value Set Using Curvature Ex-
amination 164
8.2.5 Extended Algorithm Including Frequency Interval 165
8.2.6 Example: gmC-Filter 166
8.2.6.1 Circuit Description 166
8.2.6.2 Experimental Results 168
8.3 Nonlinear Static Systems under Parameter Tolerances 168
8.3.1 Algorithm 168
8.3.2 Outer Enclosure 169
8.3.2.1 Start Intervals 171
8.3.2.2 Solution SpaceDeviation 172
8.3.3 Inner Enclosure 173
8.3.4 Example: Differential Pair 173
8.4 Nonlinear Dynamic Systems with Nominal Parameters 176
8.4.1 State Space Description 177
8.4.2 Algorithm 177
8.4.2.1 Nonlinear Mapping of State Space Descriptions 177
8.4.2.2 Sampling the State Space 179
8.4.2.3 Obtaining the Linear Mapping Matrices 182
8.4.2.4 Adjustment of the Operating Point 184
8.4.2.5 Step Size Control 184
Contents ix
8.4.3 Transient Error Stimuli Generation 185
8.4.4 Example: Log-Domain-Filter 186
8.4.4.1 Verification Results 187
8.5 Conclusions 189
References 189
9
A Low Power BiCMOS 1 GHz Super-Regenerative Transceiver for ISM 193
Applications
Catherine Dehollain, Norbert Joehl, Michel Declercq, Patrick Favre, Philippe Deval,
Alexandre Vouilloz
9.0.1 Explanation of the approach followed 194
9.1 Basic principles of super-regeneration 195
9.2 Selection of the oscillator circuit 198
9.2.1 LC oscillator 198
9.2.2 Inductor choice 200
9.2.3 Oscillator operating modes 200
9.3 Receiver performance optimization 201
9.3.1 Adjustment of the oscillator tail current 202
9.3.2 Improved harmonic oscillator circuit 202
9.4 Overall receiver architecture 203
9.4.1 Receiver isolation amplifier and oscillator schematics 204
9.5 Transmitter architecture 206
9.5.1 Transmitter Power Amplifier schematics 206

9.6 The Sampled Phase-Locked Loop 207
9.7 The complete Transceiver circuit and its performance 209
9.7.1 Measurement results 209
9.7.1.1 Receiver sensitivity 209
9.7.1.2 Receiver selectivity 210
9.7.1.3 Performance summary 211
9.8 Conclusion 212
References 212
10
Low-Voltage Switched-Capacitor Filters 215
Andrea Baschirotto
10.1 Standard structures for low-voltage SC circuits 219
10.2 Improved solutions for low-voltage SC circuits 223
10.2.1 On-chip supply voltage multiplier 225
10.2.2 On-chip clock voltage multiplier 226
10.2.3 Switched-opamp techniques 227
10.3 Circuit level considerations 231
10.3.1 Opamp design 231
10.3.2 Common-mode feedback (CMFB) design 236
10.3.3 Reduction of charge loss due to voltage spikes 238
10.4 A SOA SC filter design example 239
10.5 Open issues and future developments 244