Low-Power Audio DAC With miniDSP and 2.5-W Mono Class-D Speaker Amplifier

113 Pages·2014·1.54 MB·English

TLV320DAC3120
www.ti.com SLAS659A–NOVEMBER2009–REVISEDMAY2012
Low-Power Mono Audio DAC With Embedded miniDSP
and Mono Class-D Speaker Amplifier
CheckforSamples:TLV320DAC3120
1 INTRODUCTION
– Class-D:2.7V–5.5V(SPKVDD ≥ AVDD)
1.1 Features
• 5-mm× 5-mm 32-QFNPackage
• MonoAudioDACWith95-dBSNR
123 1.2 Applications
• Instruction-ProgrammableEmbeddedminiDSP
• Supports8-kHzto192-kHzSampleRates • PortableAudioDevices
• MonoClass-DBTLSpeakerDriver(2.5WInto • eBook
4Ω or1.6WInto8Ω)
• PortableNavigationDevices
• MonoHeadphone/LineoutDriver
• TwoSingle-Ended InputsWithOutputMixing
1.3 Description
andLevelControl
• MicrophoneBias The TLV320DAC3120 is a low-power, highly
• Built-inDigitalAudioProcessingBlocksWith integrated, high-performance mono DAC with 24-bit
User-ProgrammableBiquad, FIR Filters, and monoplayback.
DRC
The device integrates several analog features, such
• DigitalSine-WaveGeneratorfor Beepsand
as a microphone bias, headphone drivers, and a
Clicks(PRB_P25)
mono speaker driver capable of driving a 4-Ω load.
• ProgrammableDigitalAudioProcessorfor
The TLV320DAC3120 has a fully programmable
BassBoost/Treble/EQWithuptoSixBiquads
miniDSP for digital audio processing. The digital
forPlayback
audio data format is programmable to work with
• PinControlor RegisterControl forDigital
popular audio standard protocols (I2S, left/right-
PlaybackVolume-Control Settings
justified) in master, slave, DSP, and TDM modes.
• IntegratedPLLUsedforProgrammableDigital
Bass boost, treble, or EQ can be supported by the
AudioProcessor
• I2S,Left-Justified, Right-Justified,DSP,and programmable digital-signal processing block. An on-
TDMAudioInterfaces chip PLL provides the high-speed clock needed by
• I2CControlWith RegisterAuto-Increment the digital signal-processing block. The volume level
can be controlled by either a pin control or by register
• FullPower-Down Control
control. The audio functions are controlled using the
• PowerSupplies:
I2Cserialbus.
– Analog:2.7V–3.6V
– DigitalCore:1.65V–1.95V The TLV320DAC3120 is available in a 32-pin QFN
– DigitalI/O:1.1V–3.6V package.
1
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof
TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
MATLABisatrademarkofTheMathWorks,Inc.
2
Allothertrademarksarethepropertyoftheirrespectiveowners.
3
PRODUCTIONDATAinformationiscurrentasofpublicationdate.Productsconformto Copyright©2009–2012,TexasInstrumentsIncorporated
specifications per the terms of the Texas Instruments standard warranty. Production
processingdoesnotnecessarilyincludetestingofallparameters.
TLV320DAC3120
SLAS659A–NOVEMBER2009–REVISEDMAY2012 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage.
ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore
susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications.
AVSS AVDD HPVSS HPVDD SPKVSS SPKVSS SPKVDD SPKVDD
VOL/MICDET 7-BitADC P0/R116
Left and Right Audio Output Stage
Volume-Control Register Power Management
P0/R117
P1/R33–R34
GPIO1 GPIO
De-Pop
SDA I2C and
SCL Soft Start
Note: Normally,
MCLK is PLLinput; RC CLK
however, BCLK or
GPIO1 can also be
PLLinput.
Analog Class-D Speaker
MCLK PLL Attenuation Driver
0 dB to–78 dB
and Mute 6 dB to 24 dB
P0/R63 (0.5-dB steps) (6-dB steps)
Digital LData Mono DAC PM1IX/RE3R5 P1/R38 P1/R42 SPKP
WCLK Audio R Data Digital Vol S SPKP
miniDSP 24 dB to DAC
SDIN Processing (L+R)/2 Data Mute SPKM
and SPKM
BCLK Serial P0/R64
Analog ClassA/B
Interface Attenuation Headphone/Lineout
0 dB to–78 dB Driver
RESET and Mute 0 dB to 9 dB
(0.5-dB steps) (1-dB steps)
P1/R36 P1/R40
AIN1 HPOUT
P1/R30–R31
AIN2
P1/R46 2 V/2.5 V/AVDD
MICBIAS
IOVSS IOVDD DVSS DVDD
B0360-01
Figure1-1. Functional BlockDiagram
NOTE
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2 PACKAGE AND SIGNAL DESCRIPTIONS
2.1 Package/Ordering Information
OPERATING TRANSPORTMEDIA,
PACKAGE
PRODUCT PACKAGE TEMPERATURE ORDERINGNUMBER QUANTITY
DESIGNATOR
RANGE
TLV320DAC3120IRHBT Tapeandreel,250
TLV320DAC3120 QFN-32 RHB –40°Cto85°C
TLV320DAC3120IRHBR Tapeandreel,3000
2.2 Device Information
RHB Package
(Top View)
D D S
D D S
V M P V V M S D
K K K K K K S D
P P P P P P V V
S S S S S S D A
24 23 22 21 20 19 18 17
SPKVSS 25 16 AVSS
SPKP 26 15 NC
HPOUT 27 14 AIN2
HPVDD 28 13 AIN1
TLV320DAC3120
HPVSS 29 12 MICBIAS
NC 30 11 VOL/MICDET
RESET 31 10 SCL
GPIO1 32 9 SDA
1 2 3 4 5 6 7 8
S D D C N K K K
VS VD VD N DI CL CL CL
O O D W B M
I I
P0048-12
Table2-1. TERMINALFUNCTIONS
TERMINAL
I/O DESCRIPTION
NAME NO.
AIN1 13 I Analoginput#1routedtooutputmixer
AIN2 14 I Analoginput#2routedtooutputmixer
AVDD 17 – Analogpowersupply
AVSS 16 – Analogground
BCLK 7 I/O Audioserialbitclock
DIN 5 I Audioserialdatainput
DVDD 3 – Digitalpower–digitalcore
DVSS 18 – Digitalground
GPIO1 32 I/O General-purposeinput/outputandmultifunctionpin
HPOUT 27 O Headphone/lineoutdriveroutput
HPVDD 28 – Headphone/linedriverandPLLpower
HPVSS 29 – Headphone/linedriverandPLLground
IOVDD 2 – Interfacepower
IOVSS 1 – Interfaceground
MCLK 8 I Exterrnalmasterclock
MICBIAS 12 O Micophonebiasvoltage
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Table2-1.TERMINALFUNCTIONS(continued)
TERMINAL
I/O DESCRIPTION
NAME NO.
NC 4,15,30 – Noconnection
RESET 31 I Devicereset
SCL 10 I/O I2Ccontrol-busclockinput
SDA 9 I/O I2Ccontrol-busdatainput
SPKM 19,23 O Class-Dspeakerdriverinvertingoutput
SPKP 22,26 O Class-Dspeakerdrivernoninvertingoutput
SPKVDD 21,24 – Class-Dspeakerdriverpowersupply
SPKVSS 20,25 – Class-Dspeakerdriverpower-supplyground
VOL/MICDET 11 I Volumecontrolormicrophone/headphone/headsetdetection
WCLK 6 I/O Audioserialwordclock
3 ELECTRICAL SPECIFICATIONS
3.1 Absolute Maximum Ratings
overoperatingfree-airtemperaturerange(unlessotherwisenoted) (1)
VALUE UNIT
AVDDtoAVSS –0.3to3.9 V
DVDDtoDVSS –0.3to2.5 V
HPVDDtoHPVSS –0.3to3.9 V
SPKVDDtoSPKVSS –0.3to6 V
IOVDDtoIOVSS –0.3to3.9 V
Digitalinputvoltage IOVSS–0.3toIOVDD+0.3 V
Analoginputvoltage AVSS–0.3toAVDD+0.3 V
Operatingtemperaturerange –40to85 °C
Storagetemperaturerange –55to150 °C
Junctiontemperature(T Max) 105 °C
J
Powerdissipation (T Max–T )/R W
J A θJA
QFNpackage
R Thermalimpedance(withthermalpadsolderedtoboard) 35 °C/W
θJA
(1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings
only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating
Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.
Table3-1.System ThermalCharacteristics(1)
PowerRatingat25°C DeratingFactor PowerRatingat70°C PowerRatingat85°C
2.3W 28.57mW/°C 1W 0.6W
(1) Thisdatawastakenusing2-oz.(0.071-mmthick)traceandcopperpadthatissolderedtoaJEDEChigh-K,standard4-layer3-in.×3-
in.(7.62-cm×7.62-cm)PCB.
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3.2 Recommended Operating Conditions
overoperatingfree-airtemperaturerange(unlessotherwisenoted)
MIN NOM MAX UNIT
AVDD(1) ReferencedtoAVSS(2) 2.7 3.3 3.6
DVDD ReferencedtoDVSS(2) 1.65 1.8 1.95
V
HPVDD Power-supplyvoltagerange ReferencedtoHPVSS(2) 2.7 3.3 3.6
SPKVDD(1) ReferencedtoSPKVSS(2) 2.7 5.5
IOVDD ReferencedtoIOVSS(2) 1.1 3.3 3.6
Speakerimpedance Loadappliedacrossclass-Doutputpins(BTL) 4 Ω
Headphoneimpedance AC-coupledtoR 16 Ω
L
Analogaudiofull-scaleinput
V AVDD=3.3V,single-ended 0.707 V
I voltage RMS
Monolineoutputload
AC-coupledtoR 10 kΩ
impedance L
MCLK(3) Masterclockfrequency IOVDD=3.3V 50 MHz
SCL SCLclockfrequency 400 kHz
T Operatingfree-airtemperature –40 85 °C
A
(1) Tominimizebattery-currentleakage,theSPKVDDandSPKVDDvoltagelevelsshouldnotbebelowtheAVDDvoltagelevel.
(2) Allgroundsonboardaretiedtogether,sotheyshouldnotdifferinvoltagebymorethan0.2Vmaximumforanycombinationofground
signals.Byuseofawidetraceorgroundplane,ensurealow-impedanceconnectionbetweenHPVSSandDVSS.
(3) Themaximuminputfrequencyshouldbe50MHzforanydigitalpinusedasageneral-purposeclock.
3.3 Electrical Characteristics
At25°C,AVDD=HPVDD=IOVDD=3.3V,SPKVDD=3.6V,DVDD=1.8V,f (audio)=48kHz,
S
CODEC_CLKIN=256×f ,PLL=Off,VOL/MICDETpindisabled(unlessotherwisenoted)
S
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
INTERNALOSCILLATOR—RC_CLK
Oscillatorfrequency 8.2 MHz
VOLUMECONTROLPIN(ADC);VOL/MICDETpinenabled
VOL/MICDETpinconfiguredasvolumecontrol(page
0.5×
Inputvoltagerange 0/register116,bitD7=1andpage0/register67, 0 V
AVDD
bitD7=0)
Inputcapacitance 2 pF
Volumecontrolsteps 128 Steps
MICROPHONEBIAS
Page1/register46,bitsD1–D0=10 2.25 2.5 2.75
Voltageoutput V
Page1/register46,bitsD1–D0=01 2
At4-mAloadcurrent,page1/register46,bitsD1–D0
5
=10(MICBIAS=2.5V)
Voltageregulation mV
At4-mAloadcurrent,page1/register46,bitsD1–D0
7
=01(MICBIAS=2V)
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ElectricalCharacteristics(continued)
At25°C,AVDD=HPVDD=IOVDD=3.3V,SPKVDD=3.6V,DVDD=1.8V,f (audio)=48kHz,
S
CODEC_CLKIN=256×f ,PLL=Off,VOL/MICDETpindisabled(unlessotherwisenoted)
S
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
DACHEADPHONEOUTPUT,AC-COUPLEDLOAD=16Ω(SINGLE-ENDED),
DRIVERGAIN=0dB,PARASITICCAPACITANCE=30pF
Full-scaleoutputvoltage
Outputcommon-modesetting=1.65V 0.707 Vrms
(0dB)
SNR Signal-to-noiseratio Measuredasidle-channelnoise,A-weighted(1) (2) 80 95 dB
THD Totalharmonicdistortion 0-dBFSinput –85 –65 dB
Totalharmonicdistortion+
THD+N 0-dBFSinput –82 –60 dB
noise
Muteattenuation 87 dB
PSRR Power-supplyrejectionratio(3) RippleonHPVDD(3.3V)=200mVp-pat1kHz –62 dB
R =32Ω,THD+N≤–60dB 20
L
P Maximumoutputpower mW
O
R =16Ω,THD+N≤–60dB 60
L
DACLINEOUT(HPDriverinLineoutMode)
SNR Signal-to-noiseratio Measuredasidle-channelnoise,A-weighted 95 dB
THD Totalharmonicdistortion 0-dBFSinput,0-dBgain –86 dB
Totalharmonicdistortion+
THD+N 0-dBFSinput,0-dBgain –83 dB
noise
DACDIGITALINTERPOLATIONFILTERCHARACTERISTICS
SeeSection5.6.1.4forDACinterpolationfiltercharacteristics.
DACOUTPUTTOCLASS-DSPEAKEROUTPUT;LOAD=4Ω(DIFFERENTIAL),50pF
SPKVDD=3.6V,BTLmeasurement,CM=1.8V,
DACinput=0dBFS,class-Dgain=6dB,THD≤ 2.3
–16.5dB
Outputvoltage Vrms
SPKVDD=3.6V,BTLmeasurement,CM=1.8V,
DACinput=–2dBFS,class-Dgain=6dB,THD≤ 2.1
–20dB
SPKVDD=3.6V,BTLmeasurement,DACinput=
Output,common-mode 1.8 V
mute,CM=1.8V,class-Dgain=6dB
SPKVDD=3.6V,BTLmeasurement,class-Dgain=
SNR Signal-to-noiseratio 6dB,measuredasidle-channelnoise,A-weighted 88 dB
(withrespecttofull-scaleoutputvalueof2.3Vrms)
SPKVDD=3.6V,BTLmeasurement,DACinput=–6
THD Totalharmonicdistortion –65 dB
dBFS,CM=1.8V,class-Dgain=6dB
Totalharmonicdistortion+ SPKVDD=3.6V,BTLmeasurement,DACinput=–6
THD+N –63 dB
noise dBFS,CM=1.8V,class-Dgain=6dB
SPKVDD=3.6V,BTLmeasurement,rippleon
PSRR Power-supplyrejectionratio –44 dB
SPKVDD=200mVp-pat1kHz
Muteattenuation 110 dB
SPKVDD=3.6V,BTLmeasurement,CM=1.8V,
1
class-Dgain=18dB,THD=10%
SPKVDD=4.3V,BTLmeasurement,CM=1.8V,
P Maximumoutputpower 1.5 W
O class-Dgain=18dB,THD=10%
SPKVDD=5.5V,BTLmeasurement,CM=1.8V,
2.5
class-Dgain=18dB,THD=10%
(1) Ratioofoutputlevelwith1-kHzfull-scalesine-waveinput,totheoutputlevelwiththeinputsshort-circuited,measuredA-weightedovera
20-Hzto20-kHzbandwidthusinganaudioanalyzer.
(2) Allperformancemeasurementsdonewith20-kHzlow-passfilterand,wherenoted,A-weightedfilter.Failuretousesuchafiltermay
resultinhigherTHD+NandlowerSNRanddynamicrangereadingsthanshownintheElectricalCharacteristics.Thelow-passfilter
removesout-of-bandnoise,which,althoughnotaudible,mayaffectdynamicspecificationvalues.
(3) DACtoheadphone-outPSRRmeasurementiscalculatedasPSRR=20Xlog(∆V /∆V ).
HPL HPVDD
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ElectricalCharacteristics(continued)
At25°C,AVDD=HPVDD=IOVDD=3.3V,SPKVDD=3.6V,DVDD=1.8V,f (audio)=48kHz,
S
CODEC_CLKIN=256×f ,PLL=Off,VOL/MICDETpindisabled(unlessotherwisenoted)
S
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
DACOUTPUTTOCLASS-DSPEAKEROUTPUT;LOAD=8Ω(DIFFERENTIAL),50pF
SPKVDD=3.6V,BTLmeasurement,CM=1.8V,
DACinput=0dBFS,class-Dgain=6dB,THD≤ 2.2
–16.5dB
Outputvoltage Vrms
SPKVDD=3.6V,BTLmeasurement,CM=1.8V,
DACinput=–2dBFS,class-Dgain=6dB,THD≤ 2.1
–20dB
SPKVDD=3.6V,BTLmeasurement,DACinput=
Output,common-mode 1.8 V
mute,CM=1.8V,class-Dgain=6dB
SPKVDD=3.6V,BTLmeasurement,class-Dgain=
SNR Signal-to-noiseratio 6dB,measuredasidle-channelnoise,A-weighted 87 dB
(withrespecttofull-scaleoutputvalueof2.3Vrms)
SPKVDD=3.6V,BTLmeasurement,DACinput=–6
THD Totalharmonicdistortion –67 dB
dBFS,CM=1.8V,class-Dgain=6dB
Totalharmonicdistortion+ SPKVDD=3.6V,BTLmeasurement,DACinput=–6
THD+N –66 dB
noise dBFS,CM=1.8V,class-Dgain=6dB
PSRR Power-supplyrejectionratio(1) SPKVDD=3.6V,BTLmeasurement,rippleon –44 dB
SPKVDD=200mVp-pat1kHz
Muteattenuation 110 dB
SPKVDD=3.6V,BTLmeasurement,CM=1.8V,
0.7
class-Dgain=18dB,THD=10%
SPKVDD=4.3V,BTLmeasurement,CM=1.8V,
P Maximumoutputpower 1 W
O class-Dgain=18dB,THD=10%
SPKVDD=5.5V,BTLmeasurement,CM=1.8V,
1.6
class-Dgain=18dB,THD=10%
Output-stageleakagecurrent SPKVDD=4.3V,deviceispowereddown(power-
80 nA
fordirectbatteryconnection up-resetcondition)
DACPOWERCONSUMPTION
DACpowerconsumptionbasedperselectedprocessingblock,seeSection5.4
(1) DACtospeaker-outPSRRisadifferentialmeasurementcalculatedasPSRR=20×log(∆V /∆V ).
SPK(P+M) SPKVDD
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ElectricalCharacteristics(continued)
At25°C,AVDD=HPVDD=IOVDD=3.3V,SPKVDD=3.6V,DVDD=1.8V,f (audio)=48kHz,
S
CODEC_CLKIN=256×f ,PLL=Off,VOL/MICDETpindisabled(unlessotherwisenoted)
S
PARAMETER TESTCONDITIONS MIN TYP MAX UNIT
DIGITALINPUT/OUTPUT
Logicfamily CMOS
0.7×
I =5μA,IOVDD≥1.6V
V IH IOVDD V
IH
I =5μA,IOVDD<1.6V IOVDD
IH
0.3×
I =5μA,IOVDD≥1.6V –0.3
V IL IOVDD V
IL Logiclevel
I =5μA,IOVDD<1.6V 0
IL
0.8×
V I =2TTLloads V
OH OH IOVDD
0.1×
V I =2TTLloads V
OL OL IOVDD
Capacitiveload 10 pF
3.4 Timing Characteristics
3.4.1 I2S/LJF/RJF Timing in Master Mode
Allspecificationsat25°C,DVDD=1.8V
Note:Alltimingspecificationsaremeasuredat characterizationbutnottestedatfinaltest.
WCLK
t (WS) t
d r
BCLK
t
f
t (DI) t (DI)
S h
DIN
T0145-10
PARAMETER IOVDD=1.1V IOVDD=3.3V UNIT
MIN MAX MIN MAX
t (WS) WCLKdelay 45 20 ns
d
t(DI) DINsetup 8 6 ns
s
t (DI) DINhold 8 6 ns
h
t Risetime 25 10 ns
r
t Falltime 25 10 ns
f
Figure3-1.I2S/LJF/RJFTiminginMasterMode
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3.4.2 I2S/LJF/RJF Timing in Slave Mode
Allspecificationsat25°C,DVDD=1.8V
Note:Alltimingspecificationsaremeasuredat characterizationbutnottestedatfinaltest.
WCLK
t (WS) t
h r
t (BCLK) t (WS)
H S
BCLK
t (BCLK)
L
t (DI) t
S f
DIN
t (DI)
h
T0145-11
IOVDD=1.1V IOVDD=3.3V
PARAMETER UNIT
MIN MAX MIN MAX
t (BCLK) BCLKhighperiod 35 35 ns
H
t (BCLK) BCLKlowperiod 35 35 ns
L
t(WS) WCLKsetup 8 6 ns
s
t (WS) WCLKhold 8 6 ns
h
t(DI) DINsetup 8 6 ns
s
t (DI) DINhold 8 6 ns
h
t Risetime 4 4 ns
r
t Falltime 4 4 ns
f
Figure3-2.I2S/LJF/RJFTiminginSlaveMode
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3.4.3 DSP Timing in Master Mode
Allspecificationsat25°C,DVDD=1.8V
Note:Alltimingspecificationsaremeasuredat characterizationbutnottestedatfinaltest.
WCLK
t (WS) t (WS)
d d
t
f
BCLK
t (DI) t
S r
DIN
t (DI)
h
T0146-09
IOVDD=1.1V IOVDD=3.3V
PARAMETER UNIT
MIN MAX MIN MAX
t (WS) WCLKdelay 45 20 ns
d
t(DI) DINsetup 8 8 ns
s
t (DI) DINhold 8 8 ns
h
t Risetime 25 10 ns
r
t Falltime 25 10 ns
f
Figure3-3. DSPTiminginMasterMode
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