Low Power and Reliable SRAM Memory Cell and Array Design

154 Pages·2011·7.22 MB·English

by  Koichiro Ishibashi (auth.)

SpringerSeries in
ADVANCED MICROELECTRONICS 31
SpringerSeries in
ADVANCED MICROELECTRONICS
SeriesEditors:K.Itoh T.Lee T.Sakurai W.M.C.Sansen D.Schmitt-Landsiedel
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PleaseviewavailabletitlesinSpringerSeriesinAdvancedMicroelectronics
onserieshomepagehttp://www.springer.com/series/4076
Koichiro Ishibashi
Kenichi Osada
Editors
Low Power and Reliable
SRAM Memory Cell
and Array Design
With 141 Figures
123
Editors
Prof.KoichiroIshibashi
TheUniversityofElectro-Communications
1-5-1Chofugaoka,Chofu,Tokyo,182-8585Japan
[email protected]
Dr.KenichiOsada
HitachiLtd.
Higashi-koigakubo1-280,185-8601Kokubunji-shi,Tokyo,Japan
[email protected]
SeriesEditors:
Dr.KiyooItoh
HitachiLtd.,CentralResearchLaboratory,1-280Higashi-Koigakubo
Kokubunji-shi,Tokyo185-8601,Japan
ProfessorThomasLee
StanfordUniversity,DepartmentofElectricalEngineering,420ViaPalouMall,CIS-205
Stanford,CA94305-4070,USA
ProfessorTakayasuSakurai
CenterforCollaborativeResearch,UniversityofTokyo,7-22-1Roppongi
Minato-ku,Tokyo106-8558,Japan
ProfessorWillyM.C.Sansen
KatholiekeUniversiteitLeuven,ESAT-MICAS,KasteelparkArenberg10
3001Leuven,Belgium
ProfessorDorisSchmitt-Landsiedel
TechnischeUniversita¨tMu¨nchen,Lehrstuhlfu¨rTechnischeElektronik
Theresienstrasse90,Geba¨udeN3,80290Mu¨nchen,Germany
SpringerSeriesinAdvancedMicroelectronics ISSN1437-0387
ISBN978-3-642-19567-9 e-ISBN978-3-642-19568-6
DOI10.1007/978-3-642-19568-6
SpringerHeidelbergDordrechtLondonNewYork
LibraryofCongressControlNumber:2011935344
(cid:2)c Springer-VerlagBerlinHeidelberg2011
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Preface
As LSI industry has been growing, there appear such kinds of CMOS LSI as
Microprocessor,MCU,gatearray,ASIC,FPGA,andSOC.ThereisnoCMOSLSI
thatdoesnotusetheSRAMmemorycellarrays.ThebestreasonisthattheSRAM
can be fabricatedby the same processas logicprocess, andit doesnotneedextra
costtofabricate.Also,SRAM cellarrayoperatesfastandconsumeslowpowerin
LSI.DespitetheSRAMcellsizeislargerthantheotherRAMcellsuchasDRAM
cellandFlash,SRAMcellcontinuetobeusedinCMOSLSI,thankstothenatures
ofthecell.
Before 90 nm technology, we can design SRAM cell for CMOS LSI without
paying attention to electrical stability, so that we could get operable SRAM bit
cell only when we connect the six transistors of the cell. However, after 90 nm
technology,wemustdesignSRAMbitcellmorecarefully,becausevariabilityand
leakageoftransistorsinSRAMcellhavebecomelarge.Also,wemustpayattention
tosuchreliabilityissuesassofterrors,andNBTIatlowsupplyvoltages.
This book is focusing on the design of CMOS memory cell and memory cell
array, taking low voltage operation and reliability into consideration. The authors
arespecialistswhohaveengagedintheseissuesfortensofyearsinHitachiLtd,and
RenesasTechnologyCorporationthatiscurrentlyRenesasElectronicsCorporation.
I believe this book can help readers understand fundamentals of CMOS SRAM
memorycellandcellarraydesign,designmethodsofmemorycell,andcellarray
taking variability of transistors into considerations, thereby obtaining low power
and reliable SRAM arrays. This book also introduces new memory cell design
techniquesthosewecanapplytofutureLSItechnologiessuchasSOIdevices.
Acknowledgments
The editors and authors express special thanks to Dr. Kiyoo Itoh of Hitachi Ltd.
forencouragementineditingthisbook.WealsoappreciateDr.ToshiakiMasuhara,
Dr. Osamu Minato, Mr. Toshio Sasaki, and Dr. Toshifumi Shinohara for leading
v
vi Preface
the authors in various SRAM and SOC development projects. We would like to
appreciatemanycolleagues,whohavebeenworkingonthevariousprojectswithus.
Tokyo,April2011 KoichiroIshibashi
KenichiOsada
Contents
1 Introduction .................................................................. 1
KoichiroIshibashi
1.1 HistoryandTrendofSRAMMemoryCell............................ 1
1.2 MemoryCellDesignTechniquesandArrayDesignTechniques..... 3
References..................................................................... 4
2 FundamentalsofSRAMMemoryCell .................................... 5
KenichiOsada
2.1 SRAMCell.............................................................. 5
2.2 BasicOperationofSRAMCell ........................................ 5
2.3 ElectricalStabilityatReadOperation:
StaticNoiseMarginandˇRatio....................................... 9
Reference...................................................................... 10
3 ElectricalStability(ReadandWriteOperations)........................ 11
MasanaoYamaokaandYasumasaTsukamoto
3.1 FundamentalsofElectricalStability
onReadandWriteOperations ......................................... 11
3.2 V WindowCurve ...................................................... 16
th
3.3 SensitivityAnalysis..................................................... 19
References..................................................................... 24
4 LowPowerMemoryCellDesignTechnique.............................. 25
KenichiOsadaandMasanaoYamaoka
4.1 FundamentalsofLeakageofSRAMArray............................ 25
4.1.1 LeakageCurrentsinanSRAMofConventionalDesign...... 26
4.1.2 Gate-TunnelLeakageandGIDLCurrents..................... 26
4.2 SourceLineVoltageControlTechnique............................... 29
4.2.1 EFRSchemeforLowPowerSRAM .......................... 29
4.2.2 ChipArchitecture............................................... 29
4.2.3 Results........................................................... 31
vii
viii Contents
4.2.4 Source Line Voltage Control Technique
forSRAMEmbeddedintheApplicationProcessor .......... 32
4.3 LS-CellDesignforLow-VoltageOperation........................... 36
4.3.1 LithographicallySymmetricalMemoryCell.................. 37
References..................................................................... 40
5 Low-PowerArrayDesignTechniques ..................................... 43
KojiNii,MasanaoYamaoka,andKenichiOsada
5.1 DummyCellDesign .................................................... 45
5.1.1 ProblemwithWide-VoltageOperation........................ 45
5.1.2 BlockDiagramandOperationofVoltage-Adapted
Timing-GenerationScheme.................................... 46
5.1.3 TimingDiagramandEffectofVoltage-Adapted
Timing-GenerationScheme.................................... 48
5.1.4 PredecoderandWord-DriverCircuits ......................... 50
5.1.5 Results........................................................... 51
5.2 ArrayBoostTechnique ................................................. 54
5.3 ReadandWriteStabilityAssistingCircuits ........................... 59
5.3.1 ConceptofImprovingReadStability.......................... 59
5.3.2 VariationTolerantReadAssistCircuits ....................... 62
5.3.3 VariationTolerantWriteAssistCircuits....................... 67
5.3.4 SimulationResult............................................... 71
5.3.5 FabricationsandEvaluationsin45-nmTechnology .......... 72
5.4 Dual-PortArrayDesignTechniques................................... 74
5.4.1 AccessConflictIssueofDual-PortSRAM.................... 74
5.4.2 CircumventingAccessSchemeofSimultaneous
CommonRowActivation ...................................... 76
5.4.3 8TDual-PortCellDesign ...................................... 80
5.4.4 SimulatedButterflyCurvesforSNM.......................... 81
5.4.5 CellStabilityAnalysis.......................................... 83
5.4.6 StandbyLeakage................................................ 84
5.4.7 DesignandFabricationofTestChip........................... 84
5.4.8 MeasurementResult............................................ 86
References..................................................................... 87
6 Reliable Memory Cell Design for Environmental
Radiation-InducedFailuresinSRAM..................................... 89
EishiIbeandKenichiOsada
6.1 FundamentalsofSERinSRAMCell.................................. 90
6.2 SERCausedbyAlphaParticle......................................... 94
6.3 SERCausedbyNeutronsandItsQuantification...................... 97
6.3.1 BasicKnowledgeofTerrestrialNeutrons ..................... 97
6.3.2 OverallSystemtoQuantifySER–SECIS...................... 99
6.3.3 SimulationTechniquestoQuantifyNeutronSER ............ 99
6.3.4 PredictionsofScalingEffectsfromCORIMS ................ 102
Contents ix
6.4 EvolutionofMCUProblemsandClarificationoftheMechanism... 105
6.4.1 MCUCharacterizationbyAccelerator-Based
Experiments..................................................... 105
6.4.2 Simplified 3D Device Simulation Mixed
withCircuitSimulation......................................... 108
6.4.3 Full3DDeviceSimulationwithFour-Partial-Cell
ModelandMulti-CoupledBipolarInteraction(MCBI) ...... 112
6.5 CountermeasuresforReliableMemoryDesign ....................... 115
6.5.1 ECCErrorCorrectionandInterleaveTechnique
forMCU......................................................... 115
6.5.2 ECCArchitecture............................................... 117
6.5.3 Results........................................................... 118
References..................................................................... 119
7 FutureTechnologies ......................................................... 125
KojiNiiandMasanaoYamaoka
7.1 7T,8T,10TSRAMCell ................................................ 125
7.2 Thin-BoxFD-SOISRAM .............................................. 128
7.3 SRAMCellsforFINFET............................................... 135
References..................................................................... 137
Index .............................................................................. 139