Logic Synthesis for VLSI-Based Combined Finite State Machines: Synthesis Targeting ASICs, CPLDs and FPGAs

305 Pages·2023·4.961 MB·English

by  Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Małgorzata Mazurkiewicz, Elżbieta Kawecka

Lecture Notes in Electrical Engineering 922
Alexander Barkalov ·
Larysa Titarenko · Kamil Mielcarek ·
Małgorzata Mazurkiewicz ·
Elżbieta Kawecka
Logic Synthesis
for VLSI-Based
Combined Finite
State Machines
Synthesis Targeting ASICs, CPLDs and
FPGAs
Lecture Notes in Electrical Engineering
Volume 922
SeriesEditors
LeopoldoAngrisani,DepartmentofElectricalandInformationTechnologiesEngineering,UniversityofNapoli
FedericoII,Naples,Italy
MarcoArteaga,DepartamentdeControlyRobótica,UniversidadNacionalAutónomadeMéxico,Coyoacán,
Mexico
BijayaKetanPanigrahi,ElectricalEngineering,IndianInstituteofTechnologyDelhi,NewDelhi,Delhi,India
SamarjitChakraborty,FakultätfürElektrotechnikundInformationstechnik,TUMünchen,Munich,Germany
JimingChen,ZhejiangUniversity,Hangzhou,Zhejiang,China
ShanbenChen,MaterialsScienceandEngineering,ShanghaiJiaoTongUniversity,Shanghai,China
TanKayChen,DepartmentofElectricalandComputerEngineering,NationalUniversityofSingapore,Singapore,
Singapore
RüdigerDillmann,HumanoidsandIntelligentSystemsLaboratory,KarlsruheInstituteforTechnology,Karlsruhe,
Germany
HaibinDuan,BeijingUniversityofAeronauticsandAstronautics,Beijing,China
GianluigiFerrari,UniversitàdiParma,Parma,Italy
ManuelFerre,CentreforAutomationandRoboticsCAR(UPM-CSIC),UniversidadPolitécnicadeMadrid,
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SandraHirche,DepartmentofElectricalEngineeringandInformationScience,TechnischeUniversitätMünchen,
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FaryarJabbari,DepartmentofMechanicalandAerospaceEngineering,UniversityofCalifornia,Irvine,CA,USA
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JanuszKacprzyk,SystemsResearchInstitute,PolishAcademyofSciences,Warsaw,Poland
AlaaKhamis,GermanUniversityinEgyptElTagamoaElKhames,NewCairoCity,Egypt
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YongLi,HunanUniversity,Changsha,Hunan,China
QilianLiang,DepartmentofElectricalEngineering,UniversityofTexasatArlington,Arlington,TX,USA
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Spain
TanCherMing,CollegeofEngineering,NanyangTechnologicalUniversity,Singapore,Singapore
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· ·
Alexander Barkalov Larysa Titarenko
· ·
Kamil Mielcarek Małgorzata Mazurkiewicz
Elz˙bieta Kawecka
Logic Synthesis
for VLSI-Based Combined
Finite State Machines
Synthesis Targeting ASICs, CPLDs
and FPGAs
AlexanderBarkalov LarysaTitarenko
InstituteofMetrology,Electronics InstituteofMetrology,Electronics
andComputerScience andComputerScience
UniversityofZielonaGóra UniversityofZielonaGóra
ZielonaGóra,Poland ZielonaGóra,Poland
ChairofComputerScienceandInformation DepartmentofInfocommunications
Technology KharkovNationalUniversityofRadio
Vasyl’StusDonetskNationalUniversity Electronics
Vinnytsia,Ukraine Kharkiv,Ukraine
KamilMielcarek MałgorzataMazurkiewicz
InstituteofMetrology,Electronics InstituteofControlandComputation
andComputerScience Engineering
UniversityofZielonaGóra UniversityofZielonaGóra
ZielonaGóra,Poland ZielonaGóra,Poland
Elz˙bietaKawecka
DepartmentofInformationSystems
andComputerNetworks
FacultyofTechnology
TheJacobofParadiesUniversity
GorzówWielkopolski,Poland
ISSN 1876-1100 ISSN 1876-1119 (electronic)
LectureNotesinElectricalEngineering
ISBN 978-3-031-16026-4 ISBN 978-3-031-16027-1 (eBook)
https://doi.org/10.1007/978-3-031-16027-1
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Preface
Our time is characterized by the fact that computers and embedded systems can
be found practically in all fields of human activity. The up-to-day state of the
art in modern computer science is characterized by three major factors. The first
factorisadevelopmentandapplicationofultra-complexVLSIsuchas“system-on-
programmablechip”withbillionsoftransistorsandhundredsofmillionsofequiv-
alentgates.Thesecondfactorisadevelopmentofhardwaredescriptionlanguages
such as VHDL and Verilog permitting the specification of designs with tremen-
douscomplexness.Thethirdfactorisawideapplicationofdifferentcomputer-aided
design(CAD)toolstodesignverycomplexVLSI-basedprojectsinthesatisfactory
time.Thesethreefactorsaffectedsignificantlytheprocessofhardwaredesign.Now
thehardwaredesignisverysimilartothedevelopmentofcomputerprograms.The
mutualapplicationofhardwaredescriptionlanguagesandCADtoolsallowsconcen-
tratingthedesigner’senergyonthebasicproblemsofdesign,whereasaroutinework
remainstheprerogativeofcomputers.
Tremendousachievementsintheareaofsemiconductorelectronicsresultinthe
developmentofintegratedcircuitswithverylarge-scaleintegration(VLSI),suchas
application-specificintegratedcircuits(ASIC),complexprogrammablelogicdevices
(CPLD)andfield-programmablegatearrays(FPGA).Ourbooktargetscontrolunits
basedonthemodelofcombinedfinitestatemachine(CFSM).TheproposedCFSM
modelsandmethodsoftheirsynthesistargetASICs,CPLDsandFPGAs.Themodern
VLSI chips are so huge that enough only a single chip is enough to implement a
verycomplexdigitalsystemincludingadata-pathandacontrolunit.Becauseofthe
extremecomplexityanddifferentspecificsofmodernVLSIchips,itisveryimportant
todevelopeffectivedesignmethodstargetingparticularpropertiesoflogicalelements
inuse.
Asitisknown,anydigitalsystemcanberepresentedasacompositionofadata-
pathandacontrolunit(CU).Logiccircuitsofoperationalblocksformingadata-path
haveregularstructures.ItallowsusingstandardlibraryelementsofCADtools(such
ascounters,multibitadders,multipliers,multiplexers,decodersandsoon)fortheir
design.Acontrolunitcoordinatestheinterplayofothersystemblocksproducinga
sequenceofcontrolsignals.Thesecontrolsignalscauseexecutingsomeoperations
v
vi Preface
inadata-path.Asarule,controlunitshaveirregularstructures.Itmakesprocessof
their design very sophisticated. Many important features of a digital system, such
ashardwareamount,performanceandpowerconsumption,dependtoalargeextent
on characteristics of its CU. Therefore, to design competitive digital systems with
VLSIchips,adesignershouldhavefundamentalknowledgeintheareaofsynthesis
andoptimizationoflogiccircuitsofCUs.Asexperienceofmanyscientistsshows,
design methods used by standard industrial packages produce circuits which are
far from optimal. Especially, it is true in the case of designing complex CUs. It
meansthatadesignercouldbeforcedtodevelop hisowndesignmethods,nextto
program them and at last to combine them with standard packages to get a circuit
withdesiredcharacteristics.Tohelpsuchadesigner,thisbookisdevotedtosolution
oftheproblemsoflogicsynthesisandreductionofhardwareamountinCUs.
Inthisbook,wediscussacasewhenaCUisrepresentedbythemodelofCFSM.
The CFSMs combine features of both Mealy and Moore FSMs. They have output
signalsofbothMealyandMooretypes.TheyhavestatesofMooreFSMs.So,toopti-
mizethecircuitsofCFSMs,weproposetouseoptimizationmethodstargetingboth
MealyandMooreFSMs.Thebookcontainssomeoriginalsynthesisandoptimization
methodstargetinghardwarereductioninVLSI-basedCFSMcircuits.Thesemethods
takeintoaccountthepeculiaritiesofbothaCFSMmodelandaVLSIchipinuse.
Threegroupsofmethodsareusedforhardwarereduction:structuraldecomposition,
properstateassignmentandheterogeneousimplementation.
ThestructuraldecompositionisamethodallowingrepresentationofaCFSMlogic
circuit as a composition of functionally completed blocks. Each block is different
from other blocks by a system of implemented Boolean functions. The circuits of
theseblocksaremuchsimplerthanthecircuitofCFSMwithoutdecomposition.It
leads to increasing for the number of logic levels in the final CFSM circuit. But it
allowsrepresentingsomepartsofFSMcircuitbyregularsystemsofBooleanfunc-
tions As a result, the total number of logic elements is less for the decomposed
circuit than for its no decomposed counterpart. The proper state assignment mini-
mizesthenumbersofarguments(orproductterms,orboth)insystemsofBoolean
functions representing a CFSM logic circuit. The heterogeneous implementation
assumesthatdifferentblocksofdecomposedcircuitareimplementedusingdifferent
logicelements.Forexample,theregularpartsofthesemodelscanbeimplemented
usingembeddedmemoryblocks.Itresultsinreducingtheirregularpartofthecontrol
units described by means of Boolean functions. It permits decreasing for the total
numberofLUTsorPAL-basedmacrocellsincomparisonwithlogiccircuitsbased
onhomogenousimplementation.Inourbook,controlalgorithmsarerepresentedby
graph schemes of algorithms (GSA).Thischoice isbased on theobvious factthat
this specification provides the simple explanation of the methods proposed by the
authors.
We propose to use two new approaches for structural decomposition of CFSM
circuits. The first of them is called a twofold state assignment. The twofold state
assignment targets FPGA-based CFSMs. It is based on a partition of the set of
states by classes of states such that any Boolean function inside a class could be
implementedusingasingleLUT.Eachinternalstateisencodedintwoways:asan
Preface vii
elementofthesetofFSMstatesandasanelementofsomeclassofstates.Thefinal
circuithasthreelevelsoflogicandregularinterconnections.Thesecondapproachisa
mixedencodingofmicrooperations.ItcanbeusedforbothCPLD-andFPGA-based
CFSMs.Thismethodassumesthatsomemicrooperationsarerepresentedbyone-hot
codes,whiletheothersareconsideredaselementsofcollectionsofmicrooperations.
It allows reducing hardware in the part of CFSM circuit generating Mealy-type
microoperations. We combine the proposed methods withsuch known approaches
of structural decomposition as the replacement of logical conditions, encoding of
collectionsofmicrooperations,expansionofcodespace,nonstandardrepresentation
ofstatecodesandtransformationofobjectcodes.
The process of CFSM logic synthesis can be viewed as a transformation of a
controlalgorithmintosometablesdescribingthebehaviorofCFSMblocks.These
tablesareusedtofindthesystemsofBooleanfunctions,whichcanbeusedtoimple-
mentlogiccircuitsofparticularCFSMblocks.Inordertoimplementcorresponding
circuits, this information should be transformed using data formats of particular
industrialCADsystems.Wedonotdiscussthisstepinourbook.Ourbookcontains
alotofexamplesillustratingdesignofCFSMcircuitsbasedonusingtheproposed
methods.Someexamplesareillustratedbylogiccircuits.Themainpartofthebook
containseightchapters.
Chapter 1 provides some basic information. It is shown that control algo-
rithmscouldbeimplementedusingeithermicroprogramcontrolunitsorfinitestate
machines. The language of GSA is introduced. Next, the connections are shown
withGSAsandstatetransitiongraphsofMealy,MooreandcombinedFSMs.Clas-
sical principles are discussed for logic synthesis of Mealy and Moore FSMs. The
FSMlogiccircuitsareimplementedwithgatesandflip-flops.Next,themethodsof
synthesisformicroprogramcontrolunitsarediscussed.Thelastpartofthechapter
dealswithpeculiaritiesofcombinedFSMsandmethodsoftheirsynthesis.
Chapter 2 deals with analysis of methods of logic synthesis targeting VLSI. It
starts with analysis of evolution of logic elements. The peculiarities of synthesis
are shown for PROMs, PLAs and PALs. Next, three classes of VLSI chips are
considered, namely ASIC, CPLD and FPGA. The methods of structural decom-
position are discussed. Main idea of these methods is reduced to diminishing the
numbers of literals in systems of Boolean functions due to increasing the number
of logic levels in FSM circuits. Methods of replacement of logical conditions and
encoding of collections of microoperations are analyzed. Next, these methods are
applied for reducing hardware in ASIC-, CPLD- and FPGA-based FSM circuits.
It is shown that memory blocks allow implementing systems of regular Boolean
functions. The methods basing of classes of pseudoequivalent states are discussed
forMooreFSM.VLSI-basedstructuraldiagramsofFSMcircuitsbasedondifferent
methodsofstructuraldecompositionareshown.
Chapter 3 begins from the trivial matrix implementation of CFSM circuits. To
diminishthechipareaoccupiedbythetrivialmatrixcircuit,themethodsofstructural
decompositionareused.Inthebeginning,theCFSMwiththereplacementoflogical
conditionsissynthesized.Next,itisshownthattheareareductionispossibledueto
encodingofcollectionsofmicrooperationsofbothMealyandMooretypes.Next,the
viii Preface
methodofencodingofthefieldsofcompatiblemicrooperationsisusedtooptimize
thearearequiredforCFSMcircuit.Themethodsofoptimizationbasedontheclasses
ofpseudoequivalentstates(PES)ofMooreFSMsarediscussed.Threegroupsofthese
methodsareconsidered:theoptimalstateassignment,thecompletetransformationof
statesandthepartialtransformationofstatesintoclassesofPES.Next,themethods
of expansion of code space, nonstandard representation of state codes and refined
stateassignmentarediscussed.Thelastpartofthechapterisdevotedtotheanalysisof
differentpossiblemodelsofASIC-basedCFSMs.Thesemodelscombinedifferent
methods of structural decomposition used for both Mealy and Moore FSMs. The
examplesofsynthesisaregivenformajorityofproposedCFSMmodels.
Chapter 4 is devoted to reduction of ASIC chip areas occupied by CFSM logic
circuits.AllmethodsarebasedonusingtheclassesofPES.Itstartsfromoptimiza-
tion of CFSM with optimal state assignment. The optimization is achieved due to
replacementoflogicalconditions,encodingofcollectionsofmicrooperationsofboth
MealyandMooretypes.Next,thesemethodsareappliedforCFSMswithcomplete
transformation of states. Also, the method of encoding of the fields of compatible
microoperations is used for the hardware reduction. Next, these methods are used
foroptimizationCFSMswithpartialtransformationofstates.Thelastpartsofthe
chapteraredevotedtooptimizationbasedonexpansionofcodespaceandnonstan-
dardrepresentationofstatecodes.Theexamplesofsynthesisaregivenformajority
ofproposedCFSMmodels.
Chapter5dealswithsynthesisofCFSMsusingthehomogenousCPLDs,which
includeeitherPAL-orPLA-basedmacrocells.Itstartsfromsynthesisoftrivialsingle-
levelcircuits.ThePAL-basedcircuitsaremostlyanalyzed.Next,differentmethods
ofoptimizationcombinedwiththeoptimalstateassignmentarediscussed.Further,
themethodsarediscussedbasedonthetransformationofstatecodesintocodesof
classesofPES.Thisapproachiscombinedwithreplacementoflogicalconditions
and encoding of collections of microoperations. Next, the optimization methods
arediscussedbasedontheprimaryencodingoftheclassesofPES.Bothmethodsof
expansionofcodespaceandnonstandardrepresentationofstatecodesarediscussed.
Theyarecombinedwithothermethodsofhardwarereduction.Allproposedmethods
targetreducingthenumbersofproducttermsinsystemsofBooleanfunctionsrepre-
sentingCFSMcircuits.Theexamplesofsynthesisaregivenformajorityofproposed
CFSMmodels.
Chapter6dealswithsynthesisofCFSMsusingtheheterogeneousCPLDs,which
include PAL-based macrocells and embedded memory blocks. In the beginning,
circuitsbasedonembeddedmemoryblocksareanalyzed.Next,differentmodelsof
CFSMs with trivial state assignment are discussed. The EMBs are used to imple-
mentsystemsofregularfunctions,andPAL-basedmacrocellsimplementirregular
functions. Next, it is shown how to use EMBS for replacement of logical condi-
tions. Different optimization methods are discussed for CFSMs with optimal state
assignment.Next,theCFSMmodelsbasedontheprimaryencodingofclassesare
proposed.Theconditionsareshownallowingexecutionofproposedmethods.The
lastpartofthechapterisdevotedtosynthesismethodsbasedontransformationof
Preface ix
objectcodes.Theyarebasedontherepresentationofstatesbycollectionsofmicro-
operationsandidentifiers,aswellasrepresentationofmicrooperationsbystatesand
identifiers. All proposed methods target reducing the numbers of product terms in
systemsofBooleanfunctionsrepresentingCFSMcircuits.Theexamplesofsynthesis
aregivenformajorityofproposedCFSMmodels.
Chapter7isdevotedtothehardwarereductionbasedontransformationofstate
codes into the codes of classes of PES. The chapter starts from the complete state
transformation.ThemethodisappliedforCFSMsimplementedwitheitherhomoge-
nousorheterogeneousCPLDs.Thesemethodsareappliedifoutcomeoftheoptimal
state assignment is far from optimal. It is shown how to combine this approach
withother methods of structuraldecomposition. Next, theCFSMs withthe partial
state transformation are analyzed. It is proposed to use two codes for classes of
PES. It can be done due to a wide fan-in of PAL macrocells. Next, this approach
iscombinedwithothermethodsofstructuraldecomposition.Thesameisdonefor
CFSMs with PLA-based macrocells. Next, it is shown how to optimize hardware
sharingEMBsandmacrocellstoimplementthesamesystemsofBooleanfunctions.
Atlast,differentmethodsofobjecttransformationarediscussedforheterogeneous
CPLDs. All proposed methods target reducing the numbers of product terms in
systemsofBooleanfunctionsrepresentingCFSMcircuits.Theexamplesofsynthesis
aregivenformajorityofproposedCFSMmodels.
Chapter8isdevotedtothedesignofFPGA-basedCFSMs.Onlyheterogeneous
models are discussed. CFSM circuits are implemented using lookup table (LUT)
elementsandEMBs.Allproposedmethodstargetreducingthenumbersofarguments
insystemsofBooleanfunctionsrepresentingCFSMcircuits.Inthebeginning,the
trivial models of CFSMs are discussed. Next, it is shown how to apply different
methodsofstructuraldecompositiontoimprovethecharacteristicsofCFSMswith
trivialstateassignment.Next,theoptimizationmethodsbasedontheoptimalstate
assignmentarediscussed.Further,themethodsofstructuraldecompositionareused
for hardware reduction in CFSMs with expansion of code space and nonstandard
representation of state codes. Next, the methods of hardware reduction based on
mixed encoding of collections of microoperations is discussed. In this case, some
collectionsareencodedbyone-hotcodesandsomebybinarycodeswithminimum
amount of bits. The last part of the chapter is devoted to twofold state assignment
inCFSMs.Inthiscase,eachstateisencodedasanelementofthesetofstatesand
asanelementofsomeclassofpartitionofthesetofstates.ItleadstoCFSMcircuit
having exactly three levels of logic and regular interconnections. The examples of
synthesisaregivenformajorityofproposedCFSMmodels.
Let us point out that our book is the first book entirely devoted to the prob-
lems associated with synthesis and optimization of VLSI-based combined finite
statemachines.Wehopethatthebookwillbeinterestingandusefulforstudentsand
Ph.D.studentsintheareaofcomputerscience,aswellasfordesignersofmodern