Lifetime Reliability-aware Design of Integrated Circuits

113 Pages·2022·3.765 MB·English

by  Mohsen Raji, Behnam Ghavami

Mohsen Raji
Behnam Ghavami
Lifetime
Reliability-aware
Design
of Integrated
Circuits
Lifetime Reliability-aware Design of Integrated
Circuits
(cid:129)
Mohsen Raji Behnam Ghavami
Lifetime Reliability-aware
Design of Integrated Circuits
MohsenRaji BehnamGhavami
ShirazUniversity ShahidBahonarUniversityofKerman
Shiraz,Iran Kerman,Iran
ISBN978-3-031-15344-0 ISBN978-3-031-15345-7 (eBook)
https://doi.org/10.1007/978-3-031-15345-7
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“I want to thank my father and mother.”
Thank you.
Dedicated to my family, Zahra and Aala.
Mohsen
“I want to thank my father and mother.”
Thank you.
Dedicated to my family, Arezoo and Hiva.
Behnam
Preface
In recent decades, integrated circuits have achieved great performance and power
improvements owing to aggressive manufacturing technology downscaling. How-
ever, smaller feature sizes and higher power densities (and consequently tempera-
ture) have made modern VLSI circuits suffer from day-to-day increasing wear and
aging effects. Hence, the lifetime reliability of integrated circuits has become a
serious and growing challenge for the industry. So, it is necessary to analyze and
improvethelifetimereliabilityofdigitalcircuitssuchasflip-flopsandcombinational
circuitsasthebasiccomponentsoflarge-scaleintegratedcircuits.
This book investigates the design techniques for modern electronic systems
which are mainly used in applications requiring high reliability and safety such as
space satellites, automotive, or healthcare electronic systems. In this book, auto-
mateddesignapproachesarepresentedtoanalyzeandimprovethelifetimereliabil-
ity of electronic systems. The emphasis is on modeling techniques and computer-
aided design (CAD) algorithms for the analysis and improvement of lifetime reli-
abilityissuesinnano-scaleCMOSintegratedcircuits.
Shiraz,Iran MohsenRaji
Kerman,Iran BehnamGhavami
vii
Acknowledgment
After a decade of researching and teaching in the field of fault-tolerant computing
systems,wedecidedtowritethisbook.ThegroupsofstudentsfromShirazUniver-
sity and Shahid Bahonar University of Kerman who developed the mathematical
analysisapproaches,designalgorithms,andsoftwarepackageshavemadethemost
importantcontributionstothiswork.
The authors would like to thank Professor Hossein Pedram for keeping us
engagedandlearning.OurspecialthanksgotoourgraduatestudentsAtousaJafari,
S. Milad Ebrahimipour, and Reza Mahmoudi who developed the materials for
chapters and helped with the preparation of this book. All this would not have
beenpossiblewithouttheirvaluablesupport.
Writingthisbookwasharderthanwethoughtandmorerewardingthanwecould
haveeverimagined.Noneofthiswouldhavebeenpossiblewithoutourfamilies.
June2022 MohsenRaji
BehnamGhavami
ix
Contents
ImpactsofProcessVariationsandAgingonLifetime
ReliabilityofFlip-Flops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 AnalysisMethodology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Flip-FlopTopologiesUnderStudy. . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 TimingParametersofFlip-Flops. . . . . . . . . . . . . . . . . . . . . . . . . 3
2.3 AgingEffects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4 BTIModel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.5 ProcessVariationModel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3V DegradationAnalysisApproach. . . . . . . . . . . . . . . . . . . . . . . . . . . 7
th
4 TimingYield-AwareLifetimeReliabilityMetric. . . . . . . . . . . . . . . . . . 7
5 ExperimentalResults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1 CharacterizationSetup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.2 FFCharacterizationResults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.3 AgingImpactsonLifetimeReliability. . . . . . . . . . . . . . . . . . . . . 12
5.4 Power-Delay-ProductComparisonofFFs. . . . . . . . . . . . . . . . . . . 14
6 DiscussionandConclusions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Restructuring-BasedLifetimeReliabilityImprovement
ofNanoscaleMaster-SlaveFlip-Flops. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2 ProposedLifetimeReliabilityImprovementApproach. . . . . . . . . . . . . . 21
2.1 BasicIdea. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2 TechniqueApplicationtoTGFF. . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3 TechniqueApplicationtoTGFFV2. . . . . . . . . . . . . . . . . . . . . . . 23
2.4 TechniqueApplicationtoWPMS. . . . . . . . . . . . . . . . . . . . . . . . 24
2.5 TechniqueApplicationtoC2MOS. . . . . . . . . . . . . . . . . . . . . . . . 26
2.6 TransistorSizing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
xi
xii Contents
3 ExperimentalResults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1 CharacterizationSetup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2 LifetimeReliabilityIncrease. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.3 CostEvaluation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4 Conclusion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
LifetimeReliabilityImprovementofPulsedFlip-Flops. . . . . . . . . . . . . . 37
1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2 ProposedLifetimeImprovementApproach. . . . . . . . . . . . . . . . . . . . . . 38
2.1 BasicIdea. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.2 ApplicationoftheTechniquetoHLFF. . . . . . . . . . . . . . . . . . . . . 39
2.3 ApplicationoftheTechniquetoSDFF. . . . . . . . . . . . . . . . . . . . . 39
2.4 ApplicationofTechniquetoUSDFF. . . . . . . . . . . . . . . . . . . . . . 42
2.5 TechniqueApplicationtoXCFF. . . . . . . . . . . . . . . . . . . . . . . . . 43
3 ExperimentalResults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.1 CharacterizationSetup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.2 FFCharacterizationResults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3 LifetimeReliabilityofBothStructures. . . . . . . . . . . . . . . . . . . . . 46
3.4 LifetimeReliabilityIncrease. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.5 CostEvaluation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4 Conclusion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
GateSizing-BasedLifetimeReliabilityImprovement
ofIntegratedCircuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
2 ProposedFramework. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.1 StatisticalGateDelayModelUndertheJointEffects
ofNBTIandPV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.2 StatisticalCircuit-LevelDelayComputationConsidering
theJointEffectsofNBTIandPV. . . . . . . . . . . . . . . . . . . . . . . . 55
2.3 IncrementalCriticality-BasedStatisticalGate-Sizing
Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3 ExperimentalResults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
3.1 CircuitLifetimeReliabilityOptimization. . . . . . . . . . . . . . . . . . . 61
4 Conclusion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
JointTimingYieldandLifetimeReliabilityOptimization
ofIntegratedCircuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2 ProblemFormulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3 Gate-LevelDelayModelUndertheJointEffectsofNBTIandPV. . . . . 67
3.1 InitialGateDelayUnderPV. . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
3.2 DelayDegradationUnderJointEffectsofNBTIandPV. . . . . . . . 68
Contents xiii
4 GateSizingMethod. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.1 FirstPhase:InitialDelayOptimization. . . . . . . . . . . . . . . . . . . . . 71
4.2 SecondPhase:GuardbandOptimization. . . . . . . . . . . . . . . . . . . . 72
5 ExperimentalResults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5.1 EffectofTimingYieldOptimization. . . . . . . . . . . . . . . . . . . . . . 79
5.2 EvaluationoftheDelayDegradation-AwareGateCriticality
Metric. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6 Conclusion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
LifetimeReliabilityOptimizationAlgorithmsofIntegrated
CircuitsUsingDual-ThresholdVoltageAssignment. . . . . . . . . . . . . . . . 85
1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2 PV-andBTI-AwareGateDelayModel. . . . . . . . . . . . . . . . . . . . . . . . 87
3 Guardband-AwareLifetimeReliability(GAR)Metric. . . . . . . . . . . . . . 88
4 Dual-ThresholdVoltageAssignmentTechnique. . . . . . . . . . . . . . . . . . 90
4.1 MotivationExample. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.2 VthAssignmentTechniqueOverhead. . . . . . . . . . . . . . . . . . . . . 91
5 LifetimeReliabilityOptimizationFlow. . . . . . . . . . . . . . . . . . . . . . . . 93
5.1 ProcessVariation-andBTI-AwareCriticalityMetric. . .. . . . . . .. 93
5.2 OptimizationAlgorithm-BasedDVthAssignmentPolicy. . . . . . . . 94
6 ExperimentalResults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.1 PV-andBTI-AwareDelayDegradationModelVerification. . . . . 98
6.2 LifetimeReliabilityAnalysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.3 LifetimeReliabilityOptimization. . . . . . . . . . . . . . . . . . . . . . . . . 100
6.4 AlgorithmComputationComplexityandRuntime. . .. . . . . . . . .. 102
7 Conclusion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Index. . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107