Lecture 22- Piplelined ADCs & VCO-Based ADCs

32 Pages·2009·1.24 MB·English

EE247
Lecture 22
• Pipelined ADCs (continued)
–Effect gain stage, sub-DAC non-idealities on overall ADC
performance
• Digital calibration (continued)
• Correction for inter-stage gain nonlinearity
–Implementation
• Practical circuits
• Stage scaling
• Combining the bits
• Stage implementation
–Circuits
–Noise budgeting
• How many bits per stage?
–Algorithmic ADCs utilizing pipeline structure
–Advanced background calibration techniques
• Time Interleaved Converters
• VCO Based ADCs (guest speaker: RikkyMuller)
EECS 247-Lecture 22 Pipelined ADCs and More ©2009 Page 1
EE247
Midterm Exam Statistics
# of
Students
5
Average: 16
4 Standard Dev.: 2
Max.: 19
3 Min.: 12
2
1
0
11 12 13 14 15 16 17 18 19 20 Grade
out of 20
EECS 247-Lecture 22 Pipelined ADCs and More ©2009 Page 2
Pipeline ADC
Block Diagram
ADC DAC - +
Stage 1 Vres1 Stage 2 Vres2 Stage k
V
in B Bits B Bits B Bits
1 2 k
MSB....... ……...LSB
Align and Combine Data
Digital Output (B+B+………..B ) Bits
1 2 k
• Idea: Cascade several low resolution stages to obtain high overall resolution
(e.g. 10bit ADC can be built with series of 10 ADCs each 1-bit only!)
• Each stage performs coarse A/D conversion and computes its quantization
error, or "residue“
EECS 247-Lecture 22 Pipelined ADCs and More ©2009 Page 3
Summary So Far
Pipelined A/D Converters
Vref T/H+Gain Vref Vref Vref
V
in
B1bits 2B1eff B2bits 22B2Be2ff B3bits 2B23Be3ff ADC
• Cascade of low resolution stages
–By adding inter-stage gain= 2Beff
• No need to scale down Vref for stages down the pipe
• Reduced accuracy requirement for stages coming after stage 1
–Addition of Track & Hold function to interstage-gain (cid:198)
• Stages canoperate concurrently(cid:198)
• Throughput increased to as high as one sample per clock cycle
• Latency function of number of stages & conversion-per-stage
– Correction for circuit non-idealities
• Built-in redundancy compensate for sub-ADC inaccuracies such as
comparator offset (interstage gain: G=2Bneff, B < B )
neff n
EECS 247-Lecture 22 Pipelined ADCs and More ©2009 Page 4
Pipelined ADC
Error Correction/Calibration Summary
V a V3
OS 3
V V
IN1 RES1
+ + 22 +
-
ε
+ ADC DAC +
gain
ε ε
ADC D1 DAC
Error Correction/Calibration
ε , V Redundancy either same stage or next stage
ADC os
ε Digital adjustment
gain
ε Either sufficient component matching or digital
DAC
calibration
Inter-stage amplifier non-linearity ?
EECS 247-Lecture 22 Pipelined ADCs and More ©2009 Page 5
Inter-stage Gain Nonlinearity
• Invert gain stage non-linear polynomial
• Express error as function of V
RES1
• Push error into digital domain through backend
Ref: B. Murmann and B. E. Boser, "A 12-b, 75MS/s Pipelined ADC using Open-Loop Residue
Amplification," ISSCC Dig. Techn. Papers, pp. 328-329, 2003
EECS 247-Lecture 22 Pipelined ADCs and More ©2009 Page 6
Inter-stage Gain Nonlinearity
a V 3
3 X
V V D D
X RES1 B B,corr
23 + Backend +
-
εgain p = a3 (...) ε(DB, p2)
2 (23+ε 3)
gain
ε(D ,p )=p D 3−3p 2D 5+12p 3D 7−+...
B 2 2 B 2 B 2 B
•Pre-computed & stored in table look-up form
•p continuously estimated & updated (account for temp. & other variations)
2
Ref: B. Murmann and B. E. Boser, "A 12-b, 75MS/s Pipelined ADC using Open-Loop Residue
Amplification," ISSCC Dig. Techn. Papers, pp. 328-329, 2003
EECS 247-Lecture 22 Pipelined ADCs and More ©2009 Page 7
Inter-stage Gain Nonlinearity Compensation
Proof of Concept Evaluation Prototype
• Re-used 14-bit ADC in 0.35μm from Analog Devices [Kelly, ISSCC 2001]
• Modified only 1ststage with 3-b (cid:198)open-loop amplifier built with simple diff-pair +
eff
resistive load instead of the conventional feedback around high-gain amp
• Conventional 9-b backend, 2-bit redundancy in 1ststage
eff
• Real-time post-processor off-chip (FPGA)
Ref: B. Murmann and B. E. Boser, "A 12-b, 75MS/s Pipelined ADC using Open-Loop Residue
Amplification," ISSCC Dig. Techn. Papers, pp. 328-329, 2003
EECS 247-Lecture 22 Pipelined ADCs and More ©2009 Page 8
Measurement Results
12-bit ADC w Extra 2-bits for Calibration
(a) without calibration
RNG=0
10 RNG=1
B]
S
L 0
L [
N
I
-10
0 1000 2000 3000 4000 (b) with calibration
Code 1
(b) with calibration
0.5
10
B]
S
L 0 0
L [
N
I
-10
-0.5
0 1000 2000 3000 4000
-1
Code 0 1000 2000 3000 4000
C d
EECS 247-Lecture 22 Pipelined ADCs and More ©2009 Page 9
Combining the Bits
• Example: Three 2-bit stages, no redundancy
B=2 B=2 B=2
1 2 3
B =2 B =2
1eff 2eff
Vin Stage 1 Stage 2 Stage 3
2 D 2 D 2 D
1 2 3
D 6
out
+ +
1/22 1/22
1 1
Dout =D1+2B1eff D2+2B1eff ⋅2B2eff D3
1 1
Dout =D1+ D2+ D3
4 16
EECS 247-Lecture 22 Pipelined ADCs and More ©2009 Page 10
Combining the Bits
D XX
1 • Only bit shifts
D XX
2
D XX
3 • No arithmetic
------------
circuits needed
D DDDDDD
out
B=2 B=2 B=2
1 2 3
B =2 B =2
1eff 2eff
Vin Stage 1 Stage 2 Stage 3
D1 D2 D
3
MSB LSB
D
out[5:0]
EECS 247-Lecture 22 Pipelined ADCs and More ©2009 Page 11
Combining the Bits
Including Redundancy
• Example: Three 2-bit stages, incorporating 1- bit
redundancy in stages 1 and 2
B=3 B=3 B=2
1 2 3
B =2 B =2
1eff 2eff
Vin Stage 1 Stage 2 Stage 3
“8 Wires“
???
“6 Wires“
D
out[5:0]
EECS 247-Lecture 22 Pipelined ADCs and More ©2009 Page 12
Combining the Bits
1 1 • Bits overlap
D =D + D + D
out 1 2B1eff 2 2B1eff ⋅2B2eff 3 • Need adders
1 1
D =D + D + D
out 1 2 3
4 16 D XXX
1
D XXX
B1=3 B2=3 B3=2 2
B =2 B =2 D XX
1eff 2eff 3
------------
Vin Stage 1 Stage 2 Stage 3
D DDDDDD
D1 D2 D out
3
HADD HADD FADD HADD HADD
D
out[5:0]
EECS 247-Lecture 22 Pipelined ADCs and More ©2009 Page 13
Combining the Bits
Example
D 001
1
B=3 B=3 B=2 D 111
1 2 3 2
B =2 B =2
1eff 2eff D 10
3
Vin Stage 1 Stage 2 Stage 3 ------------
D1 D2 D Dout 011000
3
HADD HADD FADD HADD HADD
D
out[5:0]
EECS 247-Lecture 22 Pipelined ADCs and More ©2009 Page 14
Pipelined ADC
Stage Implementation
CLK φφ1 accoqnuvierret caocqnuvierret ......
φ φ φ ... 2
1 2 1
V Stage 1 Stage 2 Stage n
in
Vin T/H + G Vres
-
ADC DAC
• Each stage needs T/H hold function
• Track phase: Acquire input/residue from previous stage
• Hold phase: sub-ADC decision, compute residue
EECS 247-Lecture 22 Pipelined ADCs and More ©2009 Page 15
Stage Implementation
V V
in T/H T/H + G res
-
T/H ADC DAC
• Usually no dedicated T/H amplifier in each stage
(Except first stage in some cases – why?)
• T/H implicitely contained in stage building blocks
EECS 247-Lecture 22 Pipelined ADCs and More ©2009 Page 16
Stage Implementation
V
in V
T/H + G res
-
T/H ADC DAC
MDAC
• DAC-subtract-gain function can be lumped into
a single switched capacitor circuit
• "MDAC"
EECS 247-Lecture 22 Pipelined ADCs and More ©2009 Page 17
1.5-Bit Stage Implementation Example
D1,D0 VDAC
Ref: A. Abo, "Design for Reliability of Low-voltage,Switched-capacitor Circuits," UCB PhD Thesis,
1999
EECS 247-Lecture 22 Pipelined ADCs and More ©2009 Page 18
1.5-Bit Stage Implementation
Acquisition Cycle
Φ
1
D1,D0 VDAC
Vc=Vc =V
f s i
Q =C xV
Cs s i
Q =CxV
Cf f i
Ref: A. Abo, "Design for Reliability of Low-voltage,Switched-capacitor Circuits," UCB PhD Thesis,
1999
EECS 247-Lecture 22 Pipelined ADCs and More ©2009 Page 19
1.5-Bit Stage Implementation
Conversion Cycle
Φ
2
D1,D0 VDAC
Ref: A. Abo, "Design for Reliability of Low-voltage,Switched-capacitor Circuits," UCB PhD Thesis,
1999
EECS 247-Lecture 22 Pipelined ADCs and More ©2009 Page 20