Lecture 16- Introduction to ADCs & Sampling

37 Pages·2010·1.07 MB·English

by  Bernhard Boser

EE247
Lecture 16
•D/A Converters (continued)
–DAC reconstruction filter
•ADC Converters
–Sampling
• Sampling switch considerations
– Thermal noise due to switch resistance
– Clock jitter related non-idealities
– Sampling switch bandwidth limitations
– Switch conductance non-linearity induced distortion
• Sampling switch conductance dependence on input voltage
• Clock voltage boosters
– Sampling switch charge injection & clock feedthrough
EECS 247 Lecture 16: Data Converters-ADC Design © 2010 Page 1
Summary Last Lecture
• D/A converters
– Practical aspects of current-switched DACs
(continued)
– Segmented current-switched DACs
– DAC dynamic non-idealities
– DAC design considerations
– Self calibration techniques
• Current copiers
• Dynamic element matching
EECS 247 Lecture 16: Data Converters-DAC Design © 2010 Page 2
DAC In the Big Picture
Analog Input
• Learned to build
DACs Analog Anti-Aliasing
Preprocessing Filter
–Convert the
incoming digital A/D Sampling
signal to analog
Conversion +Quantization
000
• DAC output 
DSP ...001...
staircase form
110
D/A "Bits to
• Some applications Conversion Staircase"
require filtering
(smoothing) of DAC
Reconstruction
output Analog
Post processing Filter
Reconstruction
filter
Analog Output
EECS 247 Lecture 16: Data Converters-ADC Design © 2010 Page 3
DAC Reconstruction Filter
B f/2
s
•Need for and
tu 1
requirements depend on pn
I C0.5
application A
D 0
0 0.5 1 1.5 2 2.5 3
1 x 106
•Tasks: c
nis 0.5
– Correct for sincdroop
0
0 0.5 1 1.5 2 2.5 3
– R(setamiro-cvaes “ea laiapsperos”ximation) tuptu 1 x 106
O
C0.5
A
D 0
0 0.5 1 1.5 2 2.5 3
Normalized Frequency f/fs
EECS 247 Lecture 16: Data Converters-ADC Design © 2010 Page 4
Reconstruction Filter Options
Reconstruction Filters
Digital SC CT
DAC
Filter Filter Filter
• Reconstruction filter options:
–Continuous-time filter only
–CT + SC filter
• SC filter possible only in combination with oversampling (signal
bandwidth B << f /2)
s
• Digital filter
–Band limits the input signal prevent aliasing
–Could also provide high-frequency pre-emphasis to compensate in-
band sinx/xamplitude droop associated with the inherent DAC S/H
function
EECS 247 Lecture 16: Data Converters-ADC Design © 2010 Page 5
DAC Reconstruction Filter
Example: Voice-Band CODEC Receive Path
Receive
Output
f= 8kHz
s fs= 8kHz fs= 128kHz fs= 128kHz GSR
Reconstruction Filter
f= 128kHz
& sinx/x Compensator s
Note: f max = 3.4kHz
sig
fDAC = 8kHz
s
sin(p f max x T )/(p f max xT)
sig s sig s
= -2.75 dB droop due to DAC sinx/x shape
Ref: D. Senderowicz et. al, “A Family of Differential NMOS Analog Circuits for PCM Codec Filter Chip,”
IEEE Journal of Solid-State Circuits,Vol.-SC-17, No. 6, pp.1014-1023, Dec. 1982.
EECS 247 Lecture 16: Data Converters-ADC Design © 2010 Page 6
Summary
D/A Converter
• D/A architecture
– Unit element –complexity proportional to 2B-excellent DNL
– Binary weighted-complexity proportional to B-poor DNL
– Segmented-unit element MSB(B )+ binary weighted LSB(B )
1 2
Complexity proportional ((2B1-1) + B ) -DNL compromise between the two
2
• Static performance
– Component matching
• Dynamic performance
– Time constants, Glitches
• DAC improvement techniques
– Symmetrical switching rather than sequential switching
– Current source self calibration
– Dynamic element matching
• Depending on the application, reconstruction filter may be needed
EECS 247 Lecture 16: Data Converters-ADC Design © 2010 Page 7
What Next?
Analog Input
• ADC Converters: Analog Anti-Aliasing
Preprocessing Filter
A/D Sampling
– Need to build
Conversion +Quantization
circuits that
"sample“ 000
DSP ...001...
110
D/A "Bits to
– Need to build
Conversion Staircase"
circuits for
amplitude Analog Reconstruction
quantization Post processing Filter
Analog Output
EECS 247 Lecture 16: Data Converters-ADC Design © 2010 Page 8
Analog-to-Digital Converters
•Two categories:
– Nyquist rate ADCs  f max ~ 0.5xf
sig sampling
• Maximum achievable signal bandwidth higher compared
to oversampled type
• Resolution limited to <14bits
– Oversampled ADCs  f max << 0.5xf
sig sampling
• Maximum achievable signal bandwidth significantly lower
compared to nyquist
• Maximum achievable resolution high (18 to 20bits!)
EECS 247 Lecture 16: Data Converters-ADC Design © 2010 Page 9
MOS Sampling Circuits
EECS 247 Lecture 16: Data Converters-ADC Design © 2010 Page 10
Ideal Sampling

• In an ideal world, zero 1
resistance sampling
v v
switches would close for IN OUT
S1
the briefest instant to
sample a continuous C
voltage v onto the
IN
capacitor C
Output Dirac-like
pulses with amplitude 
1
equal to V at the time
IN
of sampling
T=1/f
S
• In practice not realizable!
EECS 247 Lecture 16: Data Converters-ADC Design © 2010 Page 11
Ideal Track & Hold Sampling

1

v v 1
IN OUT
S1
C T=1/f
S
• V tracks input for ½ clock cycle when switch is closed
out
• Ideally acquires exactvalue of V at the instant the switch opens
in
• "Track and Hold" (T/H) (often called Sample & Hold!)
EECS 247 Lecture 16: Data Converters-ADC Design © 2010 Page 12
Ideal T/H Sampling
Continuous time
Time
kca dlo
T/H signal rT H
(Sampled-Data
Signal)
Clock
Discrete-Time
Signal
EECS 247 Lecture 15: Data Converters-DAC Design & Intro. to ADCs © 2010 Page 13
Practical Sampling
Issues

1
v v
IN OUT
M1
C
• Switch induced noise due to M1 finite channel resistance
• Clock jitter (edge variation of  )
1
• Finite R limited bandwidth finite acquisition time
sw
• R = f(V )distortion
sw in
• Switch charge injection & clock feedthrough
EECS 247 Lecture 16: Data Converters-ADC Design © 2010 Page 14
Sampling Circuit kT/C Noise

1 4kTRDf
v
IN
v v v
IN OUT OUT
M1 R S1
C C
• Switch resistance & sampling capacitor form a low-pass filter
• Noise associated with the switch resistance results in Total noise
variance= kT/C@ the output (see noise analysis in Lecture 1)
• In high resolution ADCs with such sampling circuit right at the input,
kT/C noise at times dominates overall minimum signal handling
capability (power dissipation considerations).
EECS 247 Lecture 16: Data Converters-ADC Design © 2010 Page 15
Sampling Network kT/C Noise
For ADCs sampling capacitor size is usually chosen based on having thermal
noise smaller or equal or at times slightly larger compared to quantization noise:
Assumption: Nyquist rate ADC
D2
For a Nyquist rate ADC: Total quantization noise power 
12
Choose C such that thermal noise level is less (or equal) than Q noise
k T D2
B 
C 12
2
2B1
 C12k T 
B  V 
 FS 
22B
 C12k T
B V 2
FS
EECS 247 Lecture 16: Data Converters-ADC Design © 2010 Page 16
Sampling Network kT/C Noise
2B
2
C12k T
B 2
V
FS
Required C as a Function of ADC Resolution
min
B C (V = 1V) C (V = 0.5V)
min FS min FS
8 0.003 pF 0.012 pF
12 0.8 pF 2.4 pF
14 13 pF 52 pF
16 206 pF 824 pF
20 52,800 pF 211,200 pF
The large area required for C  limit highest achievable resolution for
Nyquist rate ADCs
Oversampling results in reduction of required value for C (will be covered in
oversampled converter lectures)
EECS 247 Lecture 16: Data Converters-ADC Design © 2010 Page 17
Practical Sampling
Issues

1
v v
IN OUT
M1
C
• Switch induced noise due to M1 finite channel resistance
• Clock jitter (edge variation of  )
1
• Finite R limited bandwidth finite acquisition time
sw
• R = f(V )distortion
sw in
• Switch charge injection & clock feedthrough
EECS 247 Lecture 16: Data Converters-ADC Design © 2010 Page 18
Clock Jitter
• So far : clock signal controls sampling instants –
which we assumed to be precisely equi-distant in
time (period T)
• Real clock generator  some level of variability
• Variability in T causes errors
– "Aperture Uncertainty" or "Aperture Jitter“
• What is the effect of clock jitter on ADC
performance?
EECS 247 Lecture 16: Data Converters-ADC Design © 2010 Page 19
Clock Jitter
• Sampling jitter
x(t)
adds an error actual
sampling
voltage
time t
J
proportional to the x’(t )
0
product of (t -t )
J 0
and the derivative
of the input signal
at the sampling
nominal (ideal)
instant sampling
time t
0
EECS 247 Lecture 16: Data Converters-ADC Design © 2010 Page 20