Inverter-Based Circuit Design Techniques for Low Supply Voltages

139 Pages·2017·4.95 MB·English

by  Rakesh Kumar Palani

ACSP · Analog Circuits And Signal Processing
Rakesh Kumar Palani
Ramesh Harjani
Inverter-Based
Circuit Design
Techniques for
Low Supply
Voltages
Analog Circuits and Signal Processing
SeriesEditors:
MohammedIsmail,Dublin,USA
MohamadSawan,Montreal,Canada
Moreinformationaboutthisseriesathttp://www.springer.com/series/7381
Rakesh Kumar Palani • Ramesh Harjani
Inverter-Based Circuit
Design Techniques
for Low Supply Voltages
123
RakeshKumarPalani RameshHarjani
DepartmentofElectrical DepartmentofElectrical
andComputerEngineering andComputerEngineering
UniversityofMinnesota UniversityofMinnesota
Minneapolis,MN,USA Minneapolis,MN,USA
ISSN1872-082X ISSN2197-1854 (electronic)
AnalogCircuitsandSignalProcessing
ISBN978-3-319-46626-2 ISBN978-3-319-46628-6 (eBook)
DOI10.1007/978-3-319-46628-6
LibraryofCongressControlNumber:2016952245
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DedicatedtoLord Muruga
Preface
Rapid advances in the field of integrated circuit design has been advantageous
fromthepointofviewofcostandminiaturization.Althoughtechnologyscalingis
advantageoustodigitalcircuitsintermsofincreasedspeedandlowerpower,analog
circuitsstronglysufferfromthistrend.Thisisbecomingacrucialbottleneckinthe
realization of a system on chip in scaled technology merging high-density digital
partswithhigh-performanceanaloginterfaces.Thisisbecausescaledtechnologies
reduce the output impedance (gain) and supply voltage which limits the dynamic
range(outputswing).Onewaytomitigatethepowersupplyrestrictionsistomove
tocurrentmodecircuitdesignratherthanvoltagemodedesigns.
This thesis focuses on designing process, voltage, and temperature (PVT)-
tolerant base band circuits at lower supply voltages and in lower technologies.
Inverter amplifiers are known to have better transconductance efficiency, better
noise, and linearity performance. But inverters are prone to PVT variations and
havepoorCMRRandPSRR.Tocircumventtheproblem,wehaveproposedvarious
biasing schemes for inverters like semi-constant current biasing, constant current
biasing, and constantgm biasing. Each biasing technique has its own advantages,
like semi-constant current biasing allows to select different PMOS and NMOS
current.Thisfeatureallowforhigherinherentinverterlinearity.Similarlyconstant
currentand constantgm biasing allows for reducedPVT sensitivity. The inverter-
based OTA achieves a measured THD of (cid:2)90:6dB, SNR of 78.7dB, CMRR of
97dB, and PSRR of 61dB while operating from a nominal power of 0.9V and
at output swing of 0.9Vpp;diff in TSMC 40nm general purpose process. Further,
themeasuredthirdharmonicdistortionvariesapproximatelyby11.5dBwith120ı
variationintemperatureand9dBwithan18%variationinsupplyvoltage.
The linearity can be increased by increasing the loop gain and bandwidth in
a negative feedback circuit or by increasing the over drive voltage in open loop
architectures. However both these techniques increases the noise contribution of
the circuit. There exist a trade off between noise and linearity in analog circuits.
Tocircumventthisproblem,wehaveintroducednonlinearcancellationtechniques
andnoisefilteringtechniques.Ananalog-to-digitalconverter(ADC)driverwhichis
capableofamplifyingthecontinuoustimesignalwithagainof8andsampleonto
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viii Preface
theinputcapacitor(1pF)of110bitsuccessiveapproximationregister(SAR)ADC
isdesignedinTSMC65nmgeneralpurposeprocess.Thisexploitsthenon-linearity
cancellation in current mirror and also allows for higher bandwidth operation by
decouplingclosed loop gain from the negativefeedbackloop. The noise from the
outofbandisfilteredbeforesamplingleadingtolownoiseoperation.Themeasured
designoperatesat100MS/sandhpasanOIP3 of40dBm attheNyquistrate,noise
power spectral density of 17nV/ Hz, and inter-modulation distortion of 65dB.
The intermodulation distortion variation across ten chips is 6 and 4dB across a
temperaturevariationof120ıC.
Non-linearitycancellationisexploitedindesigningtwofilters,ananti-aliasfilter
and a continuously tunable channel select filter. Traditional active RC filters are
based on cascade of integrators. These create multiple low impedance nodes in
thecircuitwhichresultsin a highernoise.We proposea reallow passfilter-based
filterarchitectureratherthanthetraditionalintegrator-basedapproach.Further,the
entire filtering operation takes place in current domain to circumvent the power
supply limitations. This also facilitates the use of tunable non-linear metal oxide
semiconductorcapacitor(MOSCAP)asfiltercapacitors.Weintroducetechniquesof
self-compensationtousethefilterresistorandcapacitorascompensationcapacitor
for lower power. The anti-alias filter designed for 50MHz bandwidth that is
fabricated in IBM 65nm process achieves an IIP3 of 33dBm while consuming
1.56mWfrom1.2Vsupply.Thechannelselectfilteristunablefrom34to314MHz
and is fabricated in TSMC 65nm general purpose process. This filter achieves
an OIP3 of 25.24dBm at the maximum frequency while drawing 4.2mA from
1.1Vsupply.Themeasuredintermodulationdistortionvariesby5dBacross120ıC
variation in temperature and 6.5dB across a 200mV variation in power supply.
Further,thisfilterpresentsahighimpedancenodeattheinputandalowimpedance
nodeattheoutputeasingsystemintegration.
SAR ADCs are becoming popular at lower technologies as they are based on
device switching rather than amplifyingcircuits. But recentSAR ADCs that have
good energy efficiency have had relatively large input capacitance increasing the
driverpower.Wepresenta2Xtimeinterleaved(TI)SARADCwhichhasthelowest
inputcapacitanceof133fFinliterature.Thesamplingcapacitorisseparatedfrom
thecapacitivedigitaltoanalogconverter(DAC)arraybyperformingtheinputand
DACreferencesubtractioninthecurrentdomainratherthanasdonetraditionallyin
chargedomain.TheproposedADCisfabricatedinTSMC’s65nmgeneralpurpose
process and occupies an area of 0.0338mm2. The measured ADC spurious free
dynamicrange(SFDR)is57dB,andthemeasuredeffectivenumberofbits(ENOB)
atNyquistrateis7.55bitwhileusing1.55mWpowerfrom1Vsupply.
Minneapolis,MN,USA RakeshKumarPalani
RameshHarjani
Acknowledgments
There are many people who have helped, supported, and guided me to reach this
junctureinmylife,andthisthesiswillbeincompletewithoutofferingmygratitude
to them. Firstly, I would like to expressmy gratitudeto Prof. Ramesh Harjanifor
giving me the opportunity to work in his lab and guiding me through my PhD. I
amextremelythankfulforthefreedomheprovidedmetopursuetheresearchway
I liked.Butnevertheless,he alwaysknewwhatI did andadvisedmewhenhe felt
I was spending too much time on something unreasonable or chasing something
unachievable.Frommyconversationswithmyfriendsin otheruniversities,Ihave
realizedthatIhavebeenveryluckyintermsofnumberoftape-outsandthetesting
facilitiesatmydisposal.I amindebtedto Prof.Harjaniformakingthese facilities
availableto usandnothavetoworryaboutthesethings.Ihavenotonlybenefited
technically but also learned many other skills such as technical writing, making
qualitypresentations,andproposalwriting.IwouldliketothankSavitaMa’amfor
herwonderfullectureongettingthingsdone.
I would like to thank Prof. Chris Kim, Prof. Anand Gopinath, and Prof.
HubertLimforagreeingtochairmydefenseandpreliminaryoralcommittee.The
comments given by the committee during the preliminary oral exam were very
insightfulandhelpfultowardthelatterhalfofmyPhD.
I am thankful to Martin for the discussions we had and also for his help in
teaching me soldering and the use of lab equipment. I am thankful to Martin
for teaching me paper writing and presentation skills along with his grammar
correction.
Iamgratefultothemforsharingtheintenseworkloadduringthetape-outs.Iam
also thankfulto Sriharsha Vadlamani for giving me a coffee companythroughout
myPhD.ManyideasinmyPhDisevolvedfromthecoffeediscussions.
IamgratefultoDARPAforsupportingmyproject.IamthankfultotheDARPA
CLASICTeam,Prof.Danijela,Prof.DejanMarkovic,andFangLiYuan,forhelping
meinunderstandingthedigitalbackendofasoftware-definedradio.
I learned a lot during my internships at Broadcom and Qualcomm. I was able
to imbibe some of the design methodology and practices that ensure the success
of design in my project as well. I am indebted to my managers Myron Buer,
ix
x Acknowledgments
CarlMonzel,andYifeizangatBroadcomforteachingmethememorydesignand
testingwithfocusonPVTvariations.IamalsothankfulformymentorWangYan
atQualcommwhointroducedmetodiscretetimedeltasigmamodulatorsandalso
GaneshKiran,LiangDai,andDineshAlladifortechnicaldiscussions.
There are many people in the ECE Department who silently work behind the
scenes and ensure that we students always have the best possible facilities. They
ensurethatwespendminimumtimeontheadministrativeworkandfocusmostof
thetimeonourresearch.IwouldliketothankCarlosSoria,ChimaiNguyen,Dan
Dobrick,BeckyColberg,LindaJagerson,KyleDukart,JimAufderhar,PaulaBeck,
andLindaBullis.
Finally,Iamevergratefultomyparentsforbelievinginmeandsupportingme
ineveryendeavorthatI undertook.Theyalwaysensuredthebestformeandgave
me all the freedomto do whatI liked the most. My brotherhasbeen funnyand a
goodcompanionforthelastthreeyearsofmyPhD.
Isincerelythankyouall!
Contents
1 Introduction .................................................................. 1
1.1 TraditionalOperationalTransconductance ............................ 4
1.2 DifferentialPairVersusInverter........................................ 7
1.3 NonLinearityAnalysis................................................. 9
1.4 NoiseAnalysis .......................................................... 10
1.5 InverterTransconductor................................................. 11
1.6 Non-linearityCancellationTechniques................................ 13
1.7 Organization............................................................. 14
2 Biasing ........................................................................ 17
2.1 Semi-constantCurrentBiasing......................................... 17
2.1.1 OptimalNMOS-PMOSRatioing .............................. 19
2.1.2 NonLinearityCancellationinInverters ....................... 20
2.1.3 Case1:SmallInput............................................. 21
2.1.4 Case2:LargeInput............................................. 22
2.1.5 Simulation....................................................... 23
2.2 ConstantCurrentBiasing............................................... 23
2.3 Constant-gmBiasing.................................................... 25
2.4 Conclusion .............................................................. 27
3 InverterBasedOTADesign ................................................ 29
3.1 OTADesign ............................................................. 30
3.1.1 CommonModeRejectionStage ............................... 31
3.1.2 GainandDriverStage.......................................... 32
3.2 MeasurementResults ................................................... 34
3.3 Conclusion .............................................................. 39
4 ADCDriver .................................................................. 41
4.1 ADCDriver ............................................................. 42
4.2 OTADrivingLoad...................................................... 42
4.2.1 DrivingLoadCapacitorDirectly............................... 42
4.2.2 DrivingLoadCapacitorThroughResistor .................... 43
xi