Intelligent Integrated Systems: Devices, Technologies, and Architectures

499 Pages·2013·53.723 MB·\499

by  Simon Deleonibus (Editor)

INTELLIGENT
INTEGRATED SYSTEMS
TThhiiss ppaaggee iinntteennttiioonnaallllyy lleefftt bbllaannkk
Pan Stanford Series on Renewable Energy — Volume 2
Pan Stanford Series on Intelligent Nanosystems Volume 1
INTELLIGENT
INTEGRATED SYSTEMS
Devices, Technologies, and Architectures
edited by
editors
Simon Deleonibus
Preben Maegaard
Anna Krenz
Wolfgang Palz
The Rise of Modern Wind Energy
Wind Power
for the World
CRC Press
Taylor & Francis Group
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© 2013 by Taylor & Francis Group, LLC
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Version Date: 20140318
International Standard Book Number-13: 978-981-4411-43-1 (eBook - PDF)
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February28,2014 17:42 PSPBook-9inx6in 00-Deleonibus–prelims
Contents
Acknowledgements xv
Introduction:IntelligentIntegratedSystemsForwardtoZero
VariabilityandZeroPower! 1
SimonDeleonibus
I.1 ScalingandDiversifications 2
I.1.1 Moore’sLawasanArchetypeProgressLawfor
Microelectronics 3
I.1.2 BenchmarkingSeveralPossibleChannel
Materials 4
I.1.3 NewProgressLawsandParadigms 9
I.2 IntelligentIntegratedSystems:DeviceTechnologies
andArchitectures 10
PARTI: ADVANCEDSILICON-BASEDCMOSTECHNOLOGIES
1 FromPlanartoTrigateandNanowireFullyDepleted
Transistors 19
Franc¸oisAndrieu,OlivierWeber,Marie-AnneJaud,
ThomasErnst,andOlivierFaynot
1.1 Introduction 20
1.2 DefinitionofFullyDepletedDevices 21
1.2.1 Definition 21
1.2.2 CMOSTechnologyforFullyDepletedDevices 22
1.3 ElectrostaticsandScalingTheory 24
1.4 V Variability 26
T
1.4.1 V AdjustmentandMultipleV 26
T T
1.4.2 V Variability 29
T
1.4.2.1 Limitingfactors 29
1.4.2.2 ImpactofT fluctuations 31
Si
February25,2014 17:12 PSPBook-9inx6in 00-Deleonibus–prelims
vi Contents
1.5 PlanarFDSOIPerformance 33
1.5.1 CarrierMobilityBoostersonFDSOI 33
1.5.2 StaticPerformance 36
1.5.3 DynamicPerformance 36
1.5.4 ForwardandReverseBackBiasCapabilityon
UTBB 37
1.6 NanowireandTrigateTransistors 39
1.6.1 NanowireforCMOS:Motivationsand
Challenges 39
1.6.2 FabricationandControlofNanowire
MOSFETs 40
1.6.3 InterfaceandTransportOptimization 44
1.7 Conclusion 47
2 SchottkySource/DrainMOSFETs 55
EmmanuelDubois,FlorentRavaux,ZhenkunChen,
NicolasReckinger,XiaohuiTang,Jean-PierreRaskin,
MaudVinet,andLouisHutin
2.1 Introduction 56
2.2 BackgroundandChallengesAssociatedwith
Source/DrainTechnology 57
2.3 TechniquesofSchottkyBarrierModulation 59
2.3.1 PrincipleofBarrierModulation 59
2.3.2 BandBendingatDopant-SegregatedSchottky
Junctions 59
2.3.3 DifferentFlavorsofDopantSegregation 61
2.3.4 ReviewofDopantSegregationTechniques 61
2.3.4.1 Cobaltsilicide 65
2.3.4.2 Nickelsilicide 65
2.3.4.3 Platinumsilicide 68
2.3.4.4 Erbiumandytterbiumsilicides 69
2.3.4.5 PlatinumsilicideonstrainedSOI 69
2.4 IntegrationofSchottkyBarrierMOSFETs 70
2.4.1 FromMaterialEngineeringtoDevice
Integration 70
2.4.2 Dopant-SegregatedPtSiSource/Drainfor
Thin-SOICMOSTechnology 72
February25,2014 17:12 PSPBook-9inx6in 00-Deleonibus–prelims
Contents vii
2.4.3 DualMetallicSourceandDrainIntegrationon
PlanarSingle-andDouble-GateSOICMOS
Downto20nm:PerformanceandScalability
Assessment 76
2.4.4 SchottkySource/DrainDeviceIntegration:
State-of-the-ArtReview 81
2.4.4.1 pMOStransistorsbenchmarking 81
2.4.4.2 nMOStransistorsbenchmarking 82
2.5 Conclusion 86
3 AdvancesinSilicon-on-DiamondTechnology 97
Jean-PaulMazellier,JulieWidiez,MarcRabarot,
Franc¸oisAndrieu,SamuelSaada,MathieuLions,
PhilippeBergonzo,andSimonDeleonibus
3.1 Introduction 98
3.2 ThinDiamondFilmsonSilicon 99
3.2.1 MicrowavePlasmaCVDProcess 99
3.2.2 GrowthofDiamondFilms 100
3.2.3 TowardsHighNucleationDensity 103
3.2.4 ElectricalResistivityandThermalConductivity 104
3.3 SODSubstrateFabrication 106
3.3.1 FirstAttemptstoSilicon-on-Diamond(SOD)
SubstrateFabrication 106
3.3.2 Thin-FilmsSODFabrication 107
3.3.3 SmootheningtheDiamondSurface 109
3.4 SODMOSFETTechnology 112
3.4.1 TransistorProcessing 112
3.5 Conclusion 119
4 GeOI,SiGeOIandNewDevicesArchitectures 123
CyrilleLeRoyer,EmmanuelAugendre,LouisHutin,
Fre´de´ricMayer,andWilliamvandenDaele
4.1 Introduction 124
4.2 GeOIandSGOISubstrates:Fabricationand
Characterization 125
4.2.1 GeOIbySmartCutProcess 125
4.2.2 GeOIandSGOIbytheGeEnrichment
Technique 126
February25,2014 17:12 PSPBook-9inx6in 00-Deleonibus–prelims
viii Contents
4.2.3 Pseudo-MOSFETTechnique:Principleand
ResultsforSGOIWafers 127
4.2.4 GeEnrichmentwithInitialsSOIWafers 128
4.2.5 HybridGeOI–SOISubstrates 128
4.3 GeOIandSGOIMOSFET 129
4.3.1 GeandGeOICMOS 129
4.3.2 Ultra-thinGeOIpMOSFETwithAggressiveGate
Lengths 130
4.3.3 SiGe-BasedMOSFETs:TheCaseofc-SGOICMOS 133
4.4 Dual-ChannelCMOSFeaturingGeorSiGe 136
4.4.1 PlanarGeOI–SOICMOS 136
4.4.2 PlanarDual-Channel:TheCaseofc-SiGeand
t-SiCMOS 137
4.5 NovelDeviceswithSteepSlopes 140
4.5.1 ImpactIonizationMOSFET 140
4.5.1.1 Principleofoperation 140
4.5.1.2 Structuredescription 141
4.5.1.3 Operation 141
4.5.1.4 Measurements 143
4.5.1.5 Reliability 146
4.5.2 TunnelFET 148
4.5.2.1 Introduction 148
4.5.2.2 Structure,biasesandbanddiagram 149
4.5.2.3 Operationinn-andp-channelmodes 151
4.5.2.4 TFETswithlow-bandgapmaterials
(SiGeandGe) 151
4.6 Conclusion 153
5 3DMonolithicIntegration 161
MaudVinet,PerrineBatude,andShashikanthBobba
5.1 Introduction 162
5.2 StateoftheArt 164
5.2.1 LogicDevices 165
5.2.2 Memories 166
5.3 TechnologicalChallengesandPotentialSolutions 166
5.3.1 High-QualityUpperLayer 168
5.3.1.1 Seedwindowstechniques 169
5.3.1.2 Molecularwaferbonding 170
5.3.1.3 Benchmarkandconclusion 171
February25,2014 17:12 PSPBook-9inx6in 00-Deleonibus–prelims
Contents ix
5.3.2 High-PerformanceTopandBottomLayers 171
5.3.2.1 Bottom-layerlow-temperature
process 172
5.3.2.2 Thermallyrobustbottomlayer:
optimizedsilicides 173
5.3.3 3DContacts 174
5.3.4 Alignment 177
5.4 DesignandCircuitApplications 178
5.4.1 LogicDesignandLayout 178
5.4.1.1 Intra-cellstackingtransformation 179
5.4.1.2 Intra-cellfoldingtransformation 180
5.4.1.3 Cell-on-cellstackingtransformation 181
5.4.1.4 Quantifyingplanar-to-3Dlibrary
mapping 183
5.4.2 UseofElectrostaticCouplingforSRAM
Optimization 185
5.5 Conclusion 187
6 III–VQuantumWellFETs 197
SumanDatta
6.1 Introduction 197
6.2 ElectronandHoleMobilities 198
6.3 QuantumWellFETs 200
6.4 High-κDielectriconIII–VQuantumWell 203
6.5 QuantumCapacitanceLimitofIII–VQWFETs 208
6.6 III–VQWFETonSilicon 212
6.7 Conclusion 213
7 CarbonIntegratedElectronics 217
HongLi,YasinKhatami,DeblinaSarkar,JiahaoKang,
ChuanXu,WeiLiu,andKaustavBanerjee
7.1 Introduction 217
7.2 BasicPhysics 219
7.3 FabricationTechnology 225
7.3.1 CarbonNanotubeSynthesis 225
7.3.1.1 Arcdischarge 225
7.3.1.2 Laserablation 227
7.3.1.3 Chemicalvapordeposition 227