II Stacked-FET Power Amplifiers for Millimeter-Wave Applications

149 Pages·2013·2.64 MB·English

UC San Diego
UC San Diego Electronic Theses and Dissertations
Title
High-Efficiency and High-Power CMOS Power Amplifiers for Millimeter-Wave Applications /
Permalink
https://escholarship.org/uc/item/42w86205
Author
Agah, Amir
Publication Date
2013

Peer reviewed|Thesis/dissertation
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University of California
UNIVERSITY OF CALIFORNIA, SAN DIEGO

High-Efficiency and High-Power CMOS Power Amplifiers for Millimeter-Wave
Applications

A dissertation submitted in partial satisfaction of the
requirements for the degree Doctor of Philosophy

in

Electrical Engineering (Electronic Circuits and Systems)

by

Amir Agah

Committee in charge:
Professor Lawrence Larson, Chair
Professor James Buckwalter, Co-Chair
Professor Peter Asbeck
Professor Andrew Kummel
Professor Brian Keating

2013
Copyright
Amir Agah, 2013
All rights reserved.
The dissertation of Amir Agah is approved, and it is acceptable

in quality and form for publication on microfilm and electronically:

__________________________________________________

__________________________________________________

__________________________________________________

__________________________________________________
Co-Chair
__________________________________________________
Chair

University of California, San Diego

2013

iii
TABLE OF CONTENTS

Signature ................................................................................................................. iii
Table of Contents ..................................................................................................... v
List of Figures ....................................................................................................... vii
List of Tables ....................................................................................................... xiv
Acknowledgments ................................................................................................. xv
Vita ....................................................................................................................... xvii
Abstract of Dissertation ....................................................................................... xixi
I Introduction ......................................................................................................... 1
I.A. Motivation for High-Power CMOS Millimeter-Wave Power Amplifiers ......... 1
I.B. Previous Work on CMOS Millimeter-Wave Power Amplifiers ...................... 2
I.C The Need for Efficiency Enhancement Techniques in Power Amplifiers ........ 10
I.D. Dissertation Organization............................................................................ 13
II Stacked-FET Power Amplifiers for Millimeter-Wave Applications .............. 15
II.A. Introduction ................................................................................................. 15
II.B. Analysis of Stacked FET PAs ..................................................................... 17
II.C. Technology and Device Modeling ............................................................ 22
II.D. Design of Stacked FET PAs ..................................................................... 26
II.D.I 45GHz Two-Stack PA ...................................................................... 26
II.D.II. 90GHz Two-Stack PA ..................................................................... 28
II.D.III. Two-Stage PA Design .................................................................... 30
II.E. Measurements and Comparison .................................................................. 33
iv
II.E.I 45GHz Two-Stack PA ....................................................................... 33
II.E.II. 90GHz Two-Stack PA .................................................................... 37
II.E.III. Two-Stage PA Design .................................................................... 41
II.F. Conclusion ................................................................................................... 44
III Design and Analysis of Multi-Drive Stacked-FET Power Amplifiers ......... 47
III.A. Introduction .............................................................................................. 47
III.B. Effect of the Gate Resistance on Stacked-FET PAs ................................... 48
III.C. Analysis of Multi-Drive Stacked-FET PAs ................................................. 55
III.D. Design of Multi-Drive Stacked-FET PA ................................................... 61
III.E. Measurement and Comparison ................................................................... 64
III.F. Conclusion ................................................................................................ 70
IV Design of Stacked-FET Millimeter-Wave I/Q Modulator ............................ 71
IV.A. Introduction ............................................................................................ 71
IV.B. Design of Stacked-FET Digital-to-RF Converter ..................................... 73
IV.C. Measurement Results and Comparison .................................................... 77
IV.D. Conclusion ................................................................................................. 83
V Design and Analysis of Millimeter-wave Doherty Power Amplifiers ............ 85
V.A. Introduction .............................................................................................. 85
V.B. Fully integrated Doherty Power amplifier ................................................... 88
V.B.I. Review of Conventional Doherty Amplifier design ................................. 88
V.B.II. Design of a fully-integrated mm-wave Doherty PA ................................. 90
V.C. Active Phase-shift Doherty Amplifier ..................................................... 93
V.D. Slow-wave Transmission Line Structure .................................................... 99
v
V.E. Design of Mm-wave Doherty PA ........................................................... 102
V.E.I. Doherty amplifier Using Traditional and slow-waveTransmission Line
Structure ..................................................................................................... 102
V.E.II. Active Phase-shift Doherty PA Design ........................................ 108
V.F. Measurement Results and Comparison ..................................................... 110
V.G. Conclusion ................................................................................................ 117
VI Conclusion ...................................................................................................... 118
Bibliography ....................................................................................................... 122

vi
LIST OF FIGURES

Figure. 1.1. Block diagram of an outphasing transmitter ........................................... 4
Figure 1.2. Block diagram of (a) ET and (b) EER system .......................................... 6
Figure 1.3. Efficiency as a function of output power for envelope tracking system .... 7
Figure 1.4. Block diagram of Doherty Power amplifier ............................................. 8
Figure 1.5. Ideal drain efficiency of the conventional Doherty PA with different bi-
asing for the main and auxiliary amplifier. Drain current conduction angle is 110° for
class-C operation .................................................................................................... 10
Figure 1.6. PAE versus output power of recently published Q-band PAs ................. 13
Figure 1.7. PAE versus output power of recently published W-band PAs ................. 13
Figure 2.1. Schematic of the main amplifier using a stacked-FET technique ........... 17
Figure 2.2. Simulated 45-GHz waveforms of a two-stack amplifier......................... 18
Figure 2.3. Schematic of the main amplifier using a stacked-FET technique ........... 19
Figure 2.4. 45nm SOI CMOS metal stack-up ......................................................... 23
Figure 2.5. Simulated and measured amplitude of S21 for an 800μm 50𝛺 CPW ...... 24
Figure 2.6. Simulated and measured phase of S21 for an 800μm 50𝛺 CPW ............ 24
Figure 2.7. Simulated and measured, (a) S11, S22 from 10 to 110GHz (b) MSG of a
256μm NFET .......................................................................................................... 25
Figure 2.8. Schematic of the two-stack power amplifier .......................................... 26
Figure 2.9. Load line simulation for a FET with W=256μm and L=40nm ................. 27
Figure 2.10. Simulated DE, PAE and gain of the two-stage PA for different preampli-
fier circuits, S11 of the final PA stage with optimum load for different FET
geometries of CS preamplifier ................................................................................ 28
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Figure 2.11. Schematic of the two-stage power amplifier ........................................ 30
Figure 2.12. Schematic of the two-stack power amplifier ........................................ 31
Figure 2.13. Simulated S21 of (a) the high gain configuration, (b) the wide band
configuration ........................................................................................................... 32
Figure 2.14. Photomicrograph of two-stack PA ....................................................... 33
Figure 2.15. Measured and simulated S-parameters of the power amplifier biased in
class AB mode ........................................................................................................ 34
Figure 2.16. Measured output power, gain and PAE as a function of input power at
42.5GHz biased in class AB mode ........................................................................ 35
Figure 2.17. Measured peak PAE and Psat as a function of frequency ...................... 35
Figure 2.18. Measured PAE as a function of output power for four chips ................. 36
Figure 2.19. Photomicrograph of two-stack PA ...................................................... 38
Figure 2.20. Measured and simulated S-parameters of the power amplifier biased in
class AB mode ........................................................................................................ 38
Figure 2.21. Measured and simulated DE and PAE as a function of output power at 44
GHz ......................................................................................................................... 39
Figure 2.22. Measured peak PAE and Psat as a function of frequency ...................... 40
Figure 2.23. Effect of increasing the power supply voltage of the preamplifier on gain
as a function of output power .................................................................................. 40
Figure 2.24. Photomicrograph of two-stage PA ...................................................... 41
Figure 2.25. Measured S-parameters of the narrowband and wideband power amplifi-
ers ............................................................................................................................ 42
viii
Figure 2.26. Measured DE and PAE as a function of output power at 89 GHz of nar-
rowband (Figure 2.13(a)) amplifier ......................................................................... 42
Figure 2.27. Measured peak PAE and Psat of narrowband (Figure 2.13(a)) amplifier 43
Figure 2.28. Measured peak PAE, Psat and gain of wideband (Figure 2.13(b)) ampli-
fier ........................................................................................................................... 43
Figure 3.1. Schematic of an n-stack PA .................................................................... 49
Figure 3.2. Simulated and calculated |𝛼| as a function of Qi at 20, 60 and 100GHz . 52
Figure 3.3. Normalized DE of stacked-FET PA at different frequencies as a function
of number of FETs with W=256μm .......................................................................... 54
Figure 3.4. Normalized Pout of stacked-FET at different frequencies as a function of
number of FETs with W=256μm .............................................................................. 55
Figure 3.5. Normalized PAE of stacked-FET PA at different frequencies as a function
of number of FETs with W=256μm .......................................................................... 55
Figure 3.6. Schematic of multi-drive stacked-FET PA ............................................ 56
Figure 3.7. Calculated Pout/PoutFET for multi-drive stacked-FET PA and traditional
stacked-FET PA at 100GHz with W=256μm ........................................................... 59
Figure 3.8. Calculated DE/DEFET for multi-drive stacked-FET PA and traditional
stacked-FET PA at 100GHz with W=256μm ............................................................ 59
Figure 3.9. Calculated and simulated Gain/GainFET for multi-drive stacked-FET PA
and traditional stacked-FET PA at 100GHz with W=256μm .................................... 60
Figure 3.10. Calculated and simulated PAE/PAEFET for multi-drive stacked-FET PA
and traditional stacked-FET PA at 100GHz with W=256μm .................................... 61
ix