IEEE MTT-V052-I02 (2004-02)

285 Pages·2004·15.598 MB·English

by  FANTOMASPING

IEEE TRANSACTIONS ON
MICROWAVE THEORY
AND TECHNIQUES
A PUBLICATION OF THE IEEE MICROWAVE THEORY AND TECHNIQUES SOCIETY
FEBRUARY 2004 VOLUME 52 NUMBER 2 IETMAB (ISSN 0018-9480)
PAPERS
A 14-GHz 256/257 Dual-Modulus Prcscalcr With Secondary Feedback and Ils Application Lo a Monolithic CMOS
I 0.4-GHz Phase-Locked Loop .............................................. D. -1. Yang and K. K. 0 461
Elcclromagnclic 3-D Model for Active Linear Devices: Application Lo pHEMTs in the Linear Regime ...... . . .. .. .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M. Farina, L. Pierantoni, and T Rozzi 469
Novel Broad-Band Bit-Synchronization Circuit Module for Optical lnLcrconnccLions ............ . .... K. Onodera 475
Measurements of V-Band n-Typc InSb Junction Circulalors .................. Z. M. Ng, L. E. Davis, and R. Sloan 482
An RF Electronically Controlled Impedance Tuning Network Design and Its Application to an Antenna Input Impedance
Automatic Matching System ................. J. de Mingo, A. Valdovinos, A. Crespo, D. Navarro, and P Carda 489
Multiplexing of Millimeter-Wave Signals for Fiber-Radio Links by Direct Modulation of a Two-Mode Locked Fabry-Perot
Laser. . .... . ..... .. ..... .. ..... .......... .. ..... ... M. Ogusu, K. Jnagaki, Y Mizuguchi, and T Ohira 498
Efficient Elcclromagnclic Optimization of Microwave Fillers and Multiplexers Using Rational Models .. . ...... . .. .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . A. Garcfa-Lamperez, S. Llorente-Romano, M. Salazar-Palma, and T K. Sarkar 508
Effect of Reflections on Nonstationary Gyrotron Oscillations .......................... M. 1. Airila and P Kall 522
High-Efficiency W-Band GaAs Monolithic Frequency Multipliers ............ Y. Lee, J. R. East, and L. PB. Katehi 529
Temperature Dependence of Permillivily and Loss Tangent of Lithium Tantalalc al Microwave Frequencies ......... .
. . . . . . . . . . . . . . . . . . . . . . . . . . M. V. Jacob, J. G. Hartnett, J. Mazierska, V. Giordano, J. Krupka, and M. E. Tobar 536
Study of Eigcnmodcs in Periodic Waveguides Using the Lorentz Reciprocity Theorem .... D. Pissoort and F Olyslager 542
An Adjoint Variable Method for Time-Domain Transmission-Line Modeling With Fixed Structured Grids .......... .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M. H. Bakr and N. K. Nikolova 554
Enhanced QMM-BEM Solver for Three-Dimensional Multiple-Dielectric Capacitance Extraction Within the Finite
Domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . W Yu and Z. Wang 560
A Two-Dimensional Quasi-Optical Power Combining Oscillator Array With External Injection Locking ........... .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T Magath, M. Hoff, and R. Judaschke 567
A Fast Hybrid Field-Circuit Simulator for Transient Analysis of Microwave Circuits ............... . ...... . .. .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . K. Aygiin, B. C. Fischer, J. Meng, B. Shanker, and E. Michielssen 573
A Coaxial-to-Microstrip Transition for Multilayer Substrates .................... S. A. Wartenberg and Q. H. Liu 584
An Adjoint Variable Method for Sensitivity Calculations of Multiport Devices .............................. .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E. A. Soliman, M. H. Bakr, and N. K. Nikolova 589
Distributed 2-and 3-Bil W-Band MEMS Phase Shifters on Glass Substrates .. .J.-1. Hung, L. Dussopt, and G. M. Rebeiz 600
Direct Synthesis of a New Class of Bandstop Fillers .............................. S. Amari and U. Rosenberg 607
(Contents Continued on Back Cover)
+IEEE
FEBRUARY2004 VOLUME52 NUMBER2 IETMAB (ISSN0018-9480)
PAPERS
A 14-GHz 256/257 Dual-Modulus Prescaler With Secondary Feedback and Its Application to a Monolithic CMOS
10.4-GHzPhase-LockedLoop . ... ... ... ... ... ... .... ...... ... ... ... ... ... ... .. D.-J.YangandK.K.O 461
Electromagnetic3-DModelforActiveLinearDevices:ApplicationtopHEMTsintheLinearRegime ... ... ... ....
.. ... ... .... ... ... ... ... ... ... ... ... ... ... ... .... ... ... ... M.Farina,L.Pierantoni,andT.Rozzi 469
NovelBroad-BandBit-SynchronizationCircuitModuleforOpticalInterconnections. ... ... ...... ... ... . K.Onodera 475
Measurementsof -Bandn-TypeInSbJunctionCirculators... .... ..... .... ... .. Z.M.Ng,L.E.Davis,andR.Sloan 482
AnRFElectronicallyControlledImpedanceTuningNetworkDesignandItsApplicationtoanAntennaInputImpedance
AutomaticMatchingSystem... ... ..... .... ... .. J.deMingo,A.Valdovinos,A.Crespo,D.Navarro,andP.García 489
MultiplexingofMillimeter-WaveSignalsforFiber-RadioLinksbyDirectModulationofaTwo-ModeLockedFabry–Pérot
Laser. ... .... ... ... ... ... .... ..... ... ... ... ... ... .... .M.Ogusu,K.Inagaki,Y.Mizuguchi,andT.Ohira 498
EfficientElectromagneticOptimizationofMicrowaveFiltersandMultiplexersUsingRationalModels... ... ... ....
.. ... ... .... ... ... ... ... ... ..A.García-Lampérez,S.Llorente-Romano,M.Salazar-Palma,andT.K.Sarkar 508
EffectofReflectionsonNonstationaryGyrotronOscillations .. .... ... ... ...... ... ... ... .. M.I.AirilaandP.Kåll 522
High-Efficiency -BandGaAsMonolithicFrequencyMultipliers .. ... ...... ... . Y.Lee,J.R.East,andL.P.B.Katehi 529
TemperatureDependenceofPermittivityandLossTangentofLithiumTantalateatMicrowaveFrequencies. .. ... ....
.. ... ... .... ... ... ... ... ..M.V.Jacob,J.G.Hartnett,J.Mazierska,V.Giordano,J.Krupka,andM.E.Tobar 536
StudyofEigenmodesinPeriodicWaveguidesUsingtheLorentzReciprocityTheorem..... .. D.PissoortandF.Olyslager 542
AnAdjointVariableMethodforTime-DomainTransmission-LineModelingWithFixedStructuredGrids. ... ... ....
.. ... ... .... ... ... ... ... ... ... ... ... ... ... ... .... ... ... ... ... .. M.H.BakrandN.K.Nikolova 554
Enhanced QMM-BEM Solver for Three-Dimensional Multiple-Dielectric Capacitance Extraction Within the Finite
Domain.. .... ... ... ... ... ... ... ... ... .... ..... ... .... ... ... ... ... ... ... ... .. W.YuandZ.Wang 560
ATwo-DimensionalQuasi-OpticalPowerCombiningOscillatorArrayWithExternalInjectionLocking.. ... ... ....
.. ... ... .... ... ... ... ... ... ... ... ... ... ... ... .... ... ... ... T.Magath,M.Höft,andR.Judaschke 567
AFastHybridField-CircuitSimulatorforTransientAnalysisofMicrowaveCircuits . ... ... ... ... ... ... ... ....
.. ... ... .... ... ... ... ... ... ... ... ... ...K.Aygün,B.C.Fischer,J.Meng,B.Shanker,andE.Michielssen 573
ACoaxial-to-MicrostripTransitionforMultilayerSubstrates .. .... .... ..... ... ... .. S.A.WartenbergandQ.H.Liu 584
AnAdjointVariableMethodforSensitivityCalculationsofMultiportDevices... ... ... ... ... ... ... ... ... ....
.. ... ... .... ... ... ... ... ... ... ... ... ... ... ... .... ... E.A.Soliman,M.H.Bakr,andN.K.Nikolova 589
Distributed2-and3-Bit -BandMEMSPhaseShiftersonGlassSubstrates .. ....J.-J.Hung,L.Dussopt,andG.M.Rebeiz 600
DirectSynthesisofaNewClassofBandstopFilters. .. ... ... .... ..... .... ... ... ... .. S.AmariandU.Rosenberg 607
(ContentsContinuedonBackCover)
(ContentsContinuedfromFrontCover)
Harmonic-SuppressionLTCCFilterWiththeStep-ImpedanceQuarter-WavelengthOpenStub ... ..... .... ..C.-W.Tang 617
Broad-BandThree-PortandFour-PortStriplineFerriteCoupledLineCirculators. .... ..... . C.K.QueckandL.E.Davis 625
A -BandPowerAmplifierBasedontheTraveling-WavePower-Dividing/CombiningSlotted-WaveguideCircuit. ...
.. ... ... .... ... ... ... ... ... ... ... ... ... ... ... .... ... ... .. X.Jiang,S.C.Ortiz,andA.Mortazawi 633
EmployingaGroundModeltoAccuratelyCharacterizeElectronicDevicesMeasuredWithGSGProbes.. ... ... ....
.. ... ... .... ... ... ... ... ... ... ... ... ... ... ... .... ... ... T.Jamneala,P.D.Bradley,andD.A.Feld 640
ToroidalInductorsforRadio-FrequencyIntegratedCircuits ... .... ... ... ... ... ... ... ... ... ... ... ... ....
.. ... ... .... ... ... ... .. W.Y.Liu,J.Suryanarayanan,J.Nath,S.Mohammadi,L.P.B.Katehi,andM.B.Steer 646
OptimumDesignofaPredistortionRFPowerAmplifierforMulticarrierWCDMAApplications . ... ... ... ... ....
.. ... ... .... ... ... ... ... ... ... ... ... ... ... ... .... ... ... ... ... ..J.Cha,J.Yi,J.Kim,andB.Kim 655
ANovelLow-CostBeam-SteeringTechniqueBasedontheExtended-ResonancePower-DividingMethod ... ... ....
.. ... ... .... ... ... ... ... ... ... ... ... ... ... ... .... ... ... ... ... ... .A.TombakandA.Mortazawi 664
Description of Coupling Between Degenerate Modes of a Dual-Mode Microstrip Loop Resonator Using a Novel
PerturbationArrangementandItsDual-ModeBandpassFilterApplications... ... ... .... ..... ... ... ... A.Görür 671
AnAdjointVariableMethodforTime-DomainTLMWithWide-BandJohnsMatrixBoundaries.. ... ... ... ... ....
.. ... ... .... ... ... ... ... ... ... ... ... ... ... ... .... ... ... ... ... .. M.H.BakrandN.K.Nikolova 678
Designofa42-GHz200-kWGyrotronOperatingattheSecondHarmonic... ... ... ... ... ... ... ... ... ... ....
.. ... ... .... ... ... ... ... ... ... ..M.V.Kartikeyan,E.Borie,O.Drumm,S.Illy,B.Piosczyk,andM.Thumm 686
MEMS2-BitPhase-ShifterFailureModeandReliabilityConsiderationsforLarge -BandArrays. .. ... ... ... ....
.. ... ... .... ... ... ... ... ... ... ... ... ... ... ... .... ... ... ... ... ... J.G.Teti,Jr.andF.P.Darreff 693
Low-CostBiCMOSVariableGainLNAat -BandWithUltra-LowPowerConsumption..... ..F.EllingerandH.Jäckel 702
EnhancedImplementationoftheComplexImagesMethodtoStudyBoundandLeakyRegimesinLayeredPlanarPrinted
Lines. ... .... ... ... ... ... ... ...... ... ... ... ... ... .... ... . R.Rodríguez-Berral,F.Mesa,andF.Medina 709
NewBuildingBlocksforModularDesignofEllipticandSelf-EqualizedFilters.. .... ..... .. S.AmariandU.Rosenberg 721
InformationforAuthors.. ... ... ... ... ... ... ... ... ... .... ...... ... ... ... ... ... ... ... ... ... ... .... 737
CALLSFORPAPERS
SpecialIssueonMetamaterialStructures,Phenomena,andApplications. ... ... ... ... ... ...... ... ... ... ... .... 738
SpecialIssueonMultifunctionalRFSystems.. ... ... ... ... .... ... ... .... ..... ... ... ... ... ... ... ... .... 739
2004IEEECompoundSemiconductorICSymposium . ... ... .... ... ... ... .... ..... ... ... ... ... ... ... .... 740
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IEEETRANSACTIONSONMICROWAVETHEORYANDTECHNIQUES,VOL.52,NO.2,FEBRUARY2004 461
A 14-GHz 256/257 Dual-Modulus Prescaler With
Secondary Feedback and Its Application to a
Monolithic CMOS 10.4-GHz Phase-Locked Loop
Dong-Jun Yang and Kenneth K. O
Abstract—A14-GHz256/257dual-modulusprescalerisimple- [1]–[3] and a CMOS amplifier operating at 7–25 GHz [4]–[6]
mentedusingsecondaryfeedbackinthesynchronous4/5divider havebeenreported.Forphase-lockedloops(PLLs)usinglower
ona0.18- mfoundryCMOSprocess.Thedual-modulusscheme
costtechnologies,onlyonesusinganSiGeBiCMOStechnology
utilizes a 4/5 synchronous counter which adopts an traditional
havebeenreported[7],[8].Themostdifficultchallengeforin-
MOS current mode logic clocked D flip-flop. The secondary
feedbackpathslimitsignalswingtoachievehigh-speedoperation. creasingtheoperatingfrequencyofaPLLatagiventechnology
The maximum operating frequency of the prescaler is 14 GHz nodeistherealizationofadual-modulusprescalerwithasuffi-
at DD = 18V.Utilizingtheprescaler,a10.4-GHzmonolithic cientmaximumoperatingfrequency.Toincreasetheoperating
phase-lockedloop(PLL)isdemonstrated.Thevoltage-controlled
frequency of dual-modulus prescalers, a new divider architec-
oscillator (VCO) operates between 9.7–10.4 GHz. The tuning
ture employing additional feedback is proposed and demon-
range of the VCO is 690 MHz. The phase noise of the PLL and
VCO at a 3-MHz offset with vco = 49 mA is 117 and strated. The dual-modulus prescaler fabricated in a 0.18- m
119 dBc Hz, respectively. At the current consumption of CMOSprocessoperatesatupto14GHz,whichisthehighest
vco = 81 mA, the phase noise is 122 and 122 dBc Hz, operating frequency among CMOS dual-modulus prescalers.
respectively. The PLL output phase noise at a 50-kHz offset is
Usingthisprescaler,thefirstCMOSPLLwhichoperatesabove
80dBc Hz.ThePLLconsumes 31mAat DD =18V. 10GHz[9]isreported.ThePLLintegratesaVCO,aloopfilter,
Index Terms—Dual modulus prescaler, phase-locked loop anda256/257dual-modulusprescalerandallothercomponents
(PLL),phasenoise,voltage-controlledoscillator(VCO).
for PLL.
This paper is organized as follows. Section II presents the
I. INTRODUCTION dual-modulus prescaler which achieves high-speed operation
usinganadditionalfeedbackscheme.SectionIIIoverviewsthe
THERAPIDevolutionofthecommunicationsindustryhas
10-GHzPLLarchitectureanddiscussesthecircuitcomponents,
greatlyincreasedthedemandforlow-costRFcircuitsop-
the VCO, phase frequency detector (PFD), and loop filter, as
eratingatmicrowavefrequencies.Inresponsetothis,anintense
wellasavarietyofdesignissues.SectionIVdescribesthePLL
effort has been made over the last eight or nine years to de-
implementation and measurement results. Finally, the conclu-
velopRFintegratedcircuitsusinglowercostCMOSprocesses,
sionsofthispaperaregiveninSectionV.
andthisefforthasmaturedtothepointwherenumerousmanu-
facturershaveannouncedCMOSRFintegratedcircuits(RFIC)
operating at frequencies between 900 MHz and 5.8 GHz. It II. DUAL-MODULUSPRESCALER
will not be risky to speculate that, as the frequency bands at
5 GHz and below become crowded, applications at an even Thedual-modulusprescalershowninFig.1consistsofa4/5
higher frequency band will emerge. One of the issues which synchronous divider, a 64 asynchronous divider, an interface
must be addressed to bring about this is the feasibility of im- buffer between the synchronous divider and asynchronous di-
plementing inexpensive RF components operating at frequen- vider,andadivide-by-fourcircuitwhichmatchestheprescaler
cies higher than 5 GHz with sufficient performance. Work to output to the 10-MHz reference frequency. The prescaler is
resolvethisissuehasalreadystarted.Recently,CMOSvoltage- made to divide by 256/257. The last divide-by-four circuit is
controlled oscillators (VCOs) operating between 25–50 GHz fortestingthePLLwitha10-MHzreference.Becauseofthis,
thetotaldivisionratiosare1024and1028.FromFig.1,ifthe
asynchronous divider is replaced by a divide-by-256 circuit,
ManuscriptreceivedMarch26,2003;revisedSeptember30,2003.Thework the prescaler can be made to divide by 1024/1025. A swallow
ofD.-J.YangwassupportedbyMotorolaunderaPartnershipinResearchGrant.
counter controls the division ratio (4/5) of the synchronous
ThisworkwassupportedbyagrantfromTSMC.
D.-J. Yang is with the Silicon Microwave Integrated Circuits and counter. Among all the components of the PLL, the LC tank
Systems Research Group, Department of Electrical and Computer VCOisnotthelimitforthemaximumoperatingfrequency.The
Engineering, University of Florida, Gainesville, FL 32611 USA (e-mail:
dual-modulus prescaler sets the upper limit on the maximum
[email protected]).
K. K. O is with the Silicon Microwave Integrated Circuits and Systems operating frequency for a frequency synthesizer that can be
Research Group, Department of Electrical and Computer Engineering, achieved in a given technology. The interface buffer between
University of Florida, Gainesville, FL 32611 USA and also with Global
thesynchronousandasynchronousdividerarerequiredbecause
CommunicationDevices,Inc.,NorthAndover,MA01845USA.
DigitalObjectIdentifier10.1109/TMTT.2003.821918 thesedividersusedifferentpeak-to-peakswings.
0018-9480/04$20.00©2004IEEE
462 IEEETRANSACTIONSONMICROWAVETHEORYANDTECHNIQUES,VOL.52,NO.2,FEBRUARY2004
Fig.1. Blockdiagramfor1024/1028dividerusingdual-modulusprescaler.
Fig.2. Diagramofa4/5synchronousdividerwithfeedback.
Fig.3. Dflip-flop(DFF)schematic. Fig.4. Dflip-flopincludingNOR(DFF_NOR)schematic.
The synchronous divider is the most critical circuit of a operation is incorporated into the D flip-flops as shown in
prescaler because it operates at the VCO output frequency. Fig. 4. The master D flip-flop of the first synchronous divider
To increase the maximum operating frequency, the 4/5 stage contains four NMOS transistors to incorporate the NOR
synchronous divider incorporates additional feedback. The logic into the latch. Through this merging of NOR logic for
synchronous divider consists of three basic differential D dual-modulus operation into flip-flops, the delays associated
flip-flops [10]–[12] linked by forward signal paths and addi- withboththe NOR andflip-flop operationsare reduced,which
tional backward feedback paths, as illustrated in Fig. 2. The increasesthemaximumoperatingfrequency[13].
additional feedback paths are drawn with thicker lines. A D The4/5dual-modulussynchronouscounterdividestheVCO
flip-flop, which is the basic unit of a divider, shown in Fig. 3, outputbyeither4or5dependingontheswallowcountercontrol
consists of a two-stage differential latch. The main purposes signal.Inthecaseofdividingby5,theDflip-flopssustainahigh
for using the differential latch are to reduce switching noise signalstateduringthreecyclesandalowstateduringtwocycles.
in particular on the supply lines and to increase the operating Intheconventionalsynchronousdividerwithouttheadditional
frequency of the flip-flops. Also, the use of a differential feedbackpaths,theHioutputofthedifferentialDflip-flopsin-
latch eliminates the delay between output ( ) and inverted creases during the three cycles. Following this, both the NOR
output ( ). A NOR logic circuit required for the dual-modulus gate operation and discharging of the output node from Hi to
YANGANDO:DUAL-MODULUSPRESCALERWITHSECONDARYFEEDBACKANDITSAPPLICATIONTOAMONOLITHICCMOS10.4-GHzPLL 463
Fig.6. Timingdiagramofafeedbackschemeofasynchronousdivider.
Fig.7. Simulationresultcomparisonofthedivideroutputwithandwithout
feedback.
Fig.5. Basicfeedbackschemeusingdivide-by-fouroperation.
Lo must take place within the next half clock cycle. This be- same.Undertheseconditions, and areeithersimultane-
comesimpossibleathigherclockfrequencies,andtheprescaler ouslyofforon.When and areon,theriseandfalltimes
failstoproperlyfunction. of aredecreased.Thisstrengthensthetransitionof from
The additional feedback, by limiting the signal growth Hi to Lo. When both and are off, and are si-
duringthefirstthreecycles,increasesthemaximumoperating multaneouslyon,andthetransitionoftheoutput fromhigh
frequency of the prescaler. Fig. 5 illustrates the feedback to low is strengthened. During the holding periods, which are
schemeusingadivide-by-fouroperation.Inthefigure, onceagainactivatedbyCLK,thelogiclevelsof and are
of the second D flip-flop are cross connected to the inputs different.Underthiscondition,if isLo,then isoff,
of first D flip-flop or gates of and , which form the staysHi, and its levelincreases. Since is Hi, is onand
conventional divide-by-four circuit. Additionally, transistors limitsthegrowthof duringthisholdingperiod.Thisreduces
and are added in parallel to and to provide theoutputswingof .
additionalfeedbackpathsfromtheslaveofthefirstDflip-flop. Fig.7demonstratesthesimulationresultofa4/5synchronous
The additional feedback for the slave in the first D flip-flop divider with and without the additional feedback. Without the
is provided by the master latch of the second D flip-flop. The feedback,becauseofthehighoutputswing,itisimpossiblefor
feedback for the slave in the second D flip-flop is provide by thedividertoperformtheNORoperationanddischargefromHi
themasterlatchofthefirstDflip-flop.Thetransistorsinthese toLo within a 1/2cycle[see Fig.7(a)].Therefore, the divider
feedbackpathsaresmallerthanthoseoftheforwardpath. incorrectlyfunctionsat10.4GHz.Thefigureshowstwoincor-
The timing diagram in Fig. 6 shows the operation of of rectdivideoperations(incircle)duetothehighoutputswing.
Fig.5,whichisanoutputofamasterstageofthe firstD flip- Withthefeedback,becauseofthereducedpeak-to-peaksignal
flop.Duringadivide-by-fouroperation,therearetwotransition andstrengtheneddischargefromHitoLoorchargefromLoto
periods, where is changed from Hi to Lo or Lo to Hi, and Hi,thedividerfunctionsproperlyatahighoperatingfrequency,
two holding periods, where is kept at Hior Lo. , which as shown Fig. 7(b). The output swing at 15-GHz operation in
is part of the normal signal path, drives transistor and Fig.7(c)isreducedto0.5V.
ofthefeedbackpathdrivestransistor .Duringthetransition However,thefeedbackschemeincreasestheminimumoper-
periodsactivatedbyCLK,thelogiclevelof and arethe ating frequency for the divider because the drive capability of
464 IEEETRANSACTIONSONMICROWAVETHEORYANDTECHNIQUES,VOL.52,NO.2,FEBRUARY2004
pathtransistorsize.Thisistheactualdesignconditionofasyn-
chronous4/5divider.Theoperatingwindowcanbeincreasedto
10GHzwhilereducingthemaximumoperatingfrequencyto
14GHzbydecreasingthefeedbackpathtransistorsizeto 30%
ofthesignalpathtransistorsize.
III. 10.4-GHzPLL
A. OverviewofthePLL
Thedual-modulusprescalerisutilizedtoimplementaPLL.
Fig. 8. Timing diagram of the circuit with additional feedback at low
Fig.10 showsa block diagramof the CMOS PLL. It is an in-
frequencies.
teger- -type PLL [14], [15]. The PLL consists of a VCO, a
VCO buffer, quadrature outputs at 5.2 GHz, a 256/257 dual-
modulusprescaler,adivider,aphasefrequencydetector(PFD),
achargepump,andaloopfilter.ThePFDandchargepumpare
implementedforathree-statephasedetectionscheme[16].The
referencefrequencyofthePLLisaround10MHz,whichisre-
quired to tune the VCO within its operating frequency range.
TheVCObufferisdesignedtooutputa10-GHzsignalwithan
1.5-Vswingtodirectlydrivethedual-modulusprescaler.The
loopfilterissecond-orderandusestwocapacitorsandonere-
sistor,asshowninFig.10.ThePLLformsathird-ordersystem.
Thecapacitorsintheloopfilterareintegratedusingthepolysil-
icon-to-n-well MOS structure [17]. The loop bandwidth for a
third-orderPLLsystem iscloselyrelatedtothevaluesof
Fig.9. Simulationresultaccordingtofeedbackpathtransistorsize. theresistorandcapacitorswhichdeterminethepolesandzeroof
theloopfilter.Settingtheloopbandwidthisoneofthemostim-
portant stepsfor designing a PLL because the impact of VCO
thefeedbackpathexceedsthatoftheforwardpathatfrequen-
noise, reference noise, divider noise, spur rejection, and loop
ciesbelowtheminimumoperatingfrequency.Fig.8showsthe
filternoiseontheoverallPLLnoisecharacteristicsisstrongly
D flip-flop outputs and which drive the feedback tran-
influencedbytheloopbandwidthchoice.Additionally,theset-
sistor and divider transistor , respectively, for the di-
tling time of the loop and chip area of the loop filter are in-
vide-by-four circuit shown in Fig. 5. During the transition pe-
fluencedbytheloopbandwidth.Inthisdesign,theloopband-
riodswhich aremarked inFig.8,the differentialoutputsofD
widthofthePLLissetto200kHzinordertoreducetheimpact
flip-flopsareincreasedatlowerfrequenciesbecausethelonger
of noiseontheclose-inphasenoise.Thecorner/transition
transition period (shaded regions) results in a larger swing of
frequencyofVCOphasenoisefromthefrequencyregiondom-
thedifferentialoutput.Meanwhile,duringtheholdingperiods,
inatedbythe noisetothatlimitedbythermalnoiseisabout
the differential outputs of the D flip-flop are reduced at lower
500 kHz. The charge pump current, which is a determining
frequenciesduetotheincreasedfeedbackpathdrivecapability.
factoroftheloopbandwidth,canbeexternallycontrolled.
Theslavestage( )hasthemaximumdifferentialoutputa
halfclockcycleafterthemasterstage( )switches.There-
B. DesignofSubblocksofaMonolithicPLL
fore, at point A in Fig. 8, because the feedback path differen-
tialoutputs haveamuchbiggeramplitudethanthefor- VCO: TheVCOconsistsoftwocross-coupledPMOStran-
ward path differential outputs , the drive capability of sistors( and ),aPMOSbiastransistor( ),twoMOS
thefeedbacktransistor( )iscomparabletothatofthedivider varactor capacitors ( and ), two spiral inductors ( and
transistor( )aroundtheminimumoperationfrequencyeven ), and three bypass capacitors ( , , and ) shown in
thoughthetransistor islargerthanthetransistor .Below Fig. 11. The PMOS bias transistor ( ) has a common drain
the minimum operating frequency, the drive capability of connection[18].ThephasenoiseperformanceofanLC-VCOis
exceedsthatof andthedividerfailstoproperlyoperate. determinedbythetwocross-coupledtransistors( and ),
Fig.9showsthesimulatedmaximumandminimumoperating thetailtransistor( ),andparasiticresistancesoftheLCres-
frequenciesasafunctionofthefeedbacktransistorsize.The onators. The VCO exclusively uses PMOS transistors for re-
axisisthefeedbackpathtransistorsizecomparedtotheforward duced noiseandhot-carrier-inducedwhitenoise[18],[19].
pathtransistorsize(8 m).Ifthefeedbacktransistorwidthisin- In the 0.18- m CMOS process, PMOS transistors have
creased,themaximumandminimumoperatingfrequenciesare noisethatisapproximatleyoneorderofmagnitudelower.
increased. The operation window for the synchronous divider Todrivetheprescalerandpotentiallyaquadraturegenerator
is narrowed with the feedback transistor size. For the circled at highfrequencies, a bufferoperating at 10.4 GHzwhich can
region in Fig. 9, the operating window is 7 GHz, the max- providea close torail-to-rail (about1.5 V) signal swing is re-
imum frequency is 16 GHz for the synchronous 4/5 divider, quired.ThebuffercircuitisshowninFig.12.Thebufferutilizes
andthefeedbackpathtransistorsizeisabout37%ofthesignal alow- (abouttwo)LCtank( , ),aPMOSdclevelshifter
YANGANDO:DUAL-MODULUSPRESCALERWITHSECONDARYFEEDBACKANDITSAPPLICATIONTOAMONOLITHICCMOS10.4-GHzPLL 465
Fig.10. PLLblockdiagram.
Fig.13. Circuitschematicofchargepump.
differential amplifier allows the circuit to properly interface
Fig.11. Circuitschematicof10.4-GHzLCtankVCO. to the PFD using a different supply voltage ( ). By using
a higher separate supply voltage, noise injection through the
charge pump is reduced and the tuning range of the VCO is
increased. The current pump-up and -down transistors are
cascoded to mitigate the Early effect of the transistors in
the 0.18- m process technology. The charge pump circuit
generates approximately 100- A current pulses but the pump
currentcanbetunedbyalteringtothebiascircuit.
Toachievetheloopbandwidthof200kHzwhileintegrating
thecapacitorsintheloopfilter,thechargepumpcurrentwasset
to 100 Asothatthecapacitorvaluesandtheassociatedloop
filterareacanbereduced.Thevaluesof and oftheloop
filterare227.1and 14.2pF,respectively.Thesimulatedphase
marginis67 .
IV. PLLIMPLEMENTATIONANDMEASUREMENTRESULTS
Fig.12. CircuitschematicoftheVCObuffer.
A. Dual-ModulusPrescaler
( ),andNMOSamplifiers( , ).Thelow isintended As discussed, the PLL utilizes a 256/257 dual-modulus
to achieve a broad-band response using the tuned circuit. The prescaler and the output of the prescaler is further divided
PMOS transistor sets the bias point of the buffer to around a down by a divide-by-four circuit. To verify the dual-modulus
halfof (0.9V).Theresonantfrequencyoftheoutputnet- prescaleroperation,divide-by-1024and-1028operationsmust
work (Fig. 12) of the buffer consisting of spiral inductors ( to be checked while the modulus control signal is changed.
and )andloadingcapacitances( and )isabout2GHz However, the period difference between the divided-by-1024
higherthantheoperatingVCOfrequency. and divided-by-1028 signals of 0.4 nS for the 10-MHz
PFD and Charge Pump and Loop Filter Design: As men- frequencydividedsignalswith aperiod of 100nScould not
tioned, the PFD and charge pump circuit form a three-state be reliably recognized using an oscilloscope. Because of this,
phasedetectioncircuit[16],[20].Thephasefrequencydetector thedual-modulusoperationoftheprescalerwasverifiedusing
utilizes two flip-flops to produce three states such as pull-up, an HP 8503E spectrum analyzer. Fig. 14 shows the output
pull-down, and Hi-Z. The charge pump shown in Fig. 13 spectra of the divide-by-four circuit following the 256/257
can have a separate voltage supply ( ). Using a prescaler.Thesemeasuredresultsdemonstratethattheprescaler
466 IEEETRANSACTIONSONMICROWAVETHEORYANDTECHNIQUES,VOL.52,NO.2,FEBRUARY2004
Fig.17. MeasuredphasenoiseofthePLLatI =4.9mA.
Fig.14. Measuredresultsofthedual-modulusprescaler.
Fig.15. MeasuredtuningrangeoftheVCO.
Fig.18. MeasuredphasenoisespectrumofthePLL.
TABLE I
SUMMARYOFTHEPLL’SPERFORMANCE
Fig.16. MeasuredphasenoiseofthePLLandVCOatI =8.1mA.
can successfully operate up to 14 GHz versus the simulated
maximum frequency of 16 GHz. Fig. 14(a) has the peak at
13.62 MHz, which represents the 14-GHz/1028 signal. This
showsthatthedivide-by-fiveoperationofsynchronousdivider
properly functions. Fig. 14(b) shows the 14-GHz/1024 signal.
This showsthatdivide-by-four operationofa synchronous di-
videralsoworks.Indeed,thereisanexpectedoutputfrequency
shiftof 53kHz.Themeasuredminimumworkingfrequency
of prescaler is 8.2 GHz. The prescaler consumes 15 mA at
1.8 V.
B. VCOandPLL
range is about 690 MHz from 9.76 to 10.4 GHz. The on-chip
The varactor for the VCO is implemented with a polysil- spiral inductor uses a patterned ground shield (PGS) structure
icon-to-n-wellMOSstructure[17].Fig.15showsthemeasured [21],[22].Themeasuredinductanceandseriesresistance( )
tuning characteristics of the LC-VCO versus the varactor are 0.4 nH and 3.2 . The inductor quality factor is 8.2 at
control voltage between 0–1.8 V at 1.8 V. The tuning 10.4GHz[23].