Table Of ContentEEEB273 – Electronics Analysis & Design II
Learning Outcome
(13)
Able to:
• Develop the parameters and characteristics of
Ideal Op-Amps the ideal op-amp and determine the analysis
method of ideal op-amp circuits.
• Analyze and understand the characteristics of
and
the inverting op-amp, summing op-amp, and
non-inverting op-amp (including the voltage
follower).
Op-Amp Circuits
• Analyze several ideal op-amp circuits including
the difference amplifier and the
instrumentation amplifier.
(cid:1) (cid:2)
Reference: Neamen, Chapter 9
13.0) The Operational Amplifier 13.0) The Operational Amplifier(Cont)
•Op-amp (cid:1)an IC that amplifies the difference •Two input terminals:
between two input voltages and produces a single (cid:2) Inverting(negative input terminal, #1)
output (cid:2) Non–inverting(positive input terminal, #2)
•One output terminal, #3
•Requires positive and negative dc supplies for
biasing.
•Normally 20 to 30 transistors make up an op-amp.
•Typical op-amp has parameters approaching the
ideal characteristics.
(cid:1)Based on ideal concept of op-amp, a wide range
Figure 9.1: (a) Small-signal circuit symbol of op-amp; of circuit design and analysis can be considered.
(b) op-amp with positive and negative supply voltages Non-ideal op-amp effects are not considered!
(cid:3) (cid:4)
13.1) Ideal Parameters 13.1) Ideal Parameters(Cont)
•Input resistance Rbetween terminal 1 & 2 is infinite
i
(cid:1)input current at each terminal is zero.
•Output terminal acts as an ideal voltage source,
(cid:1)small-signal output resistance R is zero.
o
•A (open-loop differential voltage gain)
od
(cid:1)very large, ideally infinity.
Figure 9.2:(a) Ideal op-amp equivalent circuit and
•The output is
(b) op-amp transfer characteristics
(cid:2)Out of phase with respect to v (inverting input).
1
(cid:2)In phase with respect to v (non-inverting input).
2
(cid:5) (cid:6)
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EEEB273 – Electronics Analysis & Design II
13.1) Ideal Parameters(Cont) 13.1.1) Development of the Ideal Parameters
•Op-amp responds only to the difference between •To develop ideal op-amp parameters, the
the two input signals v and v. MOSFET small-signal equivalent circuit, as shown
1 2
(cid:2)For v = v, v = 0. in Figure 9.3, is used as a starting point.
1 2 O
(cid:2)When v = v (cid:1) 0 (cid:3)common-mode input signal.
1 2
•Common mode output signal (Common-mode
rejection) is zero.
•Most op-amps are direct-coupled devices (i.e. no
coupling capacitors are used on the input).
Therefore the input voltages v and v can be dc
1 2
voltages, which produce a dc output voltage v . Figure 9.3: (a) n-channel enhancement-mode MOSFET
O
and (b) small-signal equivalent circuit.
(cid:7) (cid:8)
13.1.1) Development of the Ideal Parameters (Cont) 13.1.1) Development of the Ideal Parameters (Cont)
•Figure 9.4shows the MOSFET equivalent circuit •Writing a KCL equation at the gate terminal
with 2 external circuit resistors R and R (feedback produces
I F
resistor), and input signal v.
I
(cid:1)This circuit is thereforecalled a feedback circuit. vI -Vgs =Vgs-vO
R R (9.1(a))
I F
which can be arranged as
v v (cid:6) 1 1 (cid:3)
I + O =V (cid:4)(cid:4) + (cid:1)(cid:1) (9.1(b))
R R gs(cid:5)R R (cid:2)
I F I F
Figure 9.4: Simplified small-signal equivalent circuit •Since input impedance to transistor is infinite, the
of a MOSFET with input and feedback resistors. current into the device is zero (i.e. I = 0).
(cid:9) g (cid:1)(cid:10)
13.1.1) Development of the Ideal Parameters (Cont) 13.1.1) Development of the Ideal Parameters (Cont)
•A KCL equation at the output node yields •The overall voltage gain of the circuit:
V -v (cid:6) 1 (cid:3)
gsR O =gmVgs (9.2(a)) v R (cid:4)(cid:4)(cid:5)1- g R (cid:1)(cid:1)(cid:2)
F O =- F (cid:215) m F
v R (cid:6) 1 (cid:3) (9.3)
which can be solved for Vgs as follows: I I (cid:4)(cid:4)1+ (cid:1)(cid:1)
(cid:5) g R (cid:2)
m F
v 1
Vgs = ROF (cid:215)(cid:4)(cid:4)(cid:5)(cid:6)R1 -gm(cid:1)(cid:1)(cid:2)(cid:3) (9.2(b)) If gain gm ovvfO th=e -traRRnFsistor goes to infinity, (t9h.e4n)
F I I
(cid:1)(cid:1)(cid:1)(cid:1)The overall voltage gain for an ideal op-amp is the
(cid:1)(cid:1) ratio of two external circuit resistors. (cid:1)(cid:2)
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EEEB273 – Electronics Analysis & Design II
13.1.1) Development of the Ideal Parameters (Cont) 13.1.1) Development of the Ideal Parameters (Cont)
•The negative sign indicates a 180 degree phase •Output Resistanceof this circuit can be
shift between the input and the output, which determined from the equivalent circuit shown in
means that input to the transistor corresponds to Figure 9.5. The input signal source is set at zero.
the inverting terminal of an op-amp.
•The voltage gain given by Equations (9.3) and
(9.4) is called a closed-loop voltage gainsince
feedback is incorporated, while A is an open-
od
loop gain.
•By letting g (cid:2) (cid:1), V (cid:1)0, i.e. the voltage at the
m gs
input terminal is said to be at virtual ground, which
is another characteristic in an ideal op-amp. Figure 9.5: Equivalent circuit for
(cid:1)(cid:3) determining output resistance. (cid:1)(cid:4)
13.1.1) Development of the Ideal Parameters (Cont) 13.1.1) Development of the Ideal Parameters (Cont)
•A KCL equation at the output node is •Using (9.7), when g (cid:2) (cid:1), then 1/R (cid:2) (cid:1) (R (cid:2) 0)
m o o
V
I =g V + x (9.5) (cid:1)(cid:1)(cid:1)(cid:1)The output resistance of the circuit with
x m gs RI +RF negative feedback included is zero. This is also
a property of an ideal op-amp.
Voltage V can be written in terms of V as
gs x
V =V (cid:4)(cid:4)(cid:6) RI (cid:1)(cid:1)(cid:3) (9.6) •Usually an op-amp is not used in open-loop
gs x(cid:5)R +R (cid:2) configuration, but with a feedback to close the
I F loop between input and output.
From (9.5) and (9.6), can be found that
I 1 1+g R •Discussion is limited to negative feedback i.e.
x = = m I (9.7) connection is from output to the inverting
V R R +R
x o I F terminal, because this produces stable circuits.
(cid:1)(cid:5) (cid:1)(cid:6)
13.1.2) Ideal Op-Amp Characteristics 13.1.2) Ideal Op-Amp Characteristics(Cont)
•The ideal op-amp characteristics resulting from Summary:
negative feedback analysis are shown in Figure 9.6 1) A : Internal differential gain (open loop gain) is
od
and summarized next. considered to be (cid:1)
2) (v –v): Differential input voltage is assumed to
2 1
be 0. If A (cid:2) (cid:1)and v is finite, then v (cid:3) v
od O 2 1
3) R: Effective input resistance is assumed to be
i
(cid:1), so input currents i and i are essentially 0
1 2
4) R: Effective output resistance is assumed to be
o
0, so output voltage is independent of any load
connected to the output.
5) Bandwidth (cid:2) (cid:1)
Figure 9.6: Parameters of the ideal op-amp. 6) CMRR: Common mode rejection ratio = (cid:1)
(cid:1)(cid:7) (cid:1)(cid:2)(cid:3)(cid:4) (cid:1)(cid:8)
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EEEB273 – Electronics Analysis & Design II
13.1.3) Practical Specifications 13.1.3) Practical Specifications(Cont)
(cid:5)(cid:6)(cid:7)(cid:8)
•Practical op-amps are not ideal, although their •R : load resistance connected to the output
L
characteristics approach those of ideal op-amps. terminal, may actually represent another op-amp.
Figure 9.7(a) is a more accurate op-amp equivalent
circuit. •Finite R and non-zero R
i O
•Output voltage swing:
(cid:2)Limited by the dc bias voltages. When v
O
reaches V+(or V_) it will saturate.
(cid:2)(cid:1)Vis between 1 to 2 V for older op-amps, or
as low as 10mV for newer CMOS op-amps.
(cid:2)To avoid distorting the output signal waveform
must be kept within linear range of operation
Figure 9.7: (a) Equivalent circuit of the op-amp
(Range of v (cid:1) V_+ (cid:1)V < v < V+-(cid:1)V)
and (b) simplified voltage transfer characteristic. (cid:1)(cid:9) O O (cid:2)(cid:10)
13.1.3) Practical Specifications(Cont) 13.2) Inverting Amplifier
•Output Currents: •Inverting amplifier (cid:1)one of most widely used op-
amp circuit.
(cid:2)Current is induced in R if v becomes either •Figure 9.8 shows the closed-loop configuration of
L O
positive or negative. this circuit. The op-amp is biased with dc voltages,
although these connections are seldom explicitly shown.
(cid:2)Maximum current that an op-amp can supply
(when v is positive) or sink(when v is
O O
negative) is limited for practical purposes.
(cid:2)Typical value of maximum current is on the
order of 20 mA.
Figure 9.8:Inverting op-amp circuit
(cid:5)(cid:6)(cid:7)(cid:8) (cid:2)(cid:1) (cid:2)(cid:2)
13.2.1) Basic Inverting Amplifier 13.2.1) Basic Inverting Amplifier(Cont)
•Circuit in Figure 9.8 is analyzed by considering the The Closed-Loop Voltage Gain
ideal equivalent circuit shown in Figure 9.9. •Defined as:
A = v / v (9.8)
v O I
•If A (cid:1) (cid:1)is assumed, then v (cid:1)v. Since v is
od 1 2 2
grounded, v must be approximately zero. This effect
1
is known as virtual ground (cid:1)essentially zero volts
but it does not provide a current path to ground.
•Therefore, from Figure 9.9
Figure 9.9:Inverting op-amp equivalent circuit i = (v –v) / R = v / R (9.9)
(cid:2)(cid:3) 1 I 1 1 I 1 (cid:2)(cid:4)
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EEEB273 – Electronics Analysis & Design II
12.2.1) Basic Inverting Amplifier(Cont) 13.2.1) Basic Inverting Amplifier(Cont)
The Closed-Loop Voltage Gain (Cont)
•Since current into the op-amp is assumed to be
zero, current i must flow through resistor R to the
1 2
output terminal, so i = i
1 2
•The output voltage is given by
v = v -i R = 0 –(v / R)R (9.10)
O 1 2 2 I 1 2
•Therefore, the closed-loop voltage gain is
A = v / v = –(R / R) (9.11)
v O I 2 1
(cid:1)(cid:1)(cid:1)(cid:1)A is a function of the resistor ratios and the
v
negative sign implies a phase reversal.
(cid:2)(cid:5) (cid:2)(cid:6)
13.2.1) Basic Inverting Amplifier(Cont) 13.2.1) Basic Inverting Amplifier(Cont)
The Input Resistance •Figure 9.10 summarizes the analysis of inverting
•Resistance as seen by the voltage source v. amplifier circuit. Since there are no coupling
I
•Due to the virtual ground, i.e. v = 0 capacitors in the op-amp circuit, the input and output
1
i = v / R voltages, as well as currents in the resistors can be
1 I 1
dc signals.
•Input resistance is then defined as
R = v / i = R (9.12)
i I 1 1
(cid:1)(cid:1)(cid:1)(cid:1)The input resistance seen by the source is a
function of R only, and is a result of the “virtual
1
ground” concept.
Figure 9.10: Currents and voltages in the inverting op-amp.
(cid:2)(cid:7) (cid:2)(cid:8)
13.2.1) Basic Inverting Amplifier(Cont) 13.2.1) Basic Inverting Amplifier(Cont)
Example 9.1 Example 9.1 (Cont)
Objective:Design an inverting amplifier with a Design Pointer: If the sinusoidal input signal
specified voltage gain. source has a nonzero output resistance, the op-
amp must be redesigned to provide the specified
Specifications:The circuit configuration to be voltage gain.
designed is shown in Figure 9.10. Design the circuit
such that the voltage gain is A = -5. Initial Solution:The input current is given by
v
Assume the op-amp is driven by an ideal sinusoidal i = v / R = v / R
1 I 1 s 1
source, v = 0.1 sin (cid:2)t(V), that can supply a
s
maximum current of 5 µA.Assume that frequency If i(max) = 5 µA, then we can write
1
(cid:2)is low so that any frequency effects can be R = v(max)/i(max) = 0.1/ 5µ= 20 k(cid:3)
1 s 1
neglected.
(cid:2)(cid:9) (cid:3)(cid:10)
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EEEB273 – Electronics Analysis & Design II
13.2.1) Basic Inverting Amplifier(Cont) 13.2.1) Basic Inverting Amplifier(Cont)
Example 9.1 (Cont) Example 9.1 (Cont)
The closed-loop gain is given by Redesign Solution:The output resistance of the
A = -R / R = -5 signal source is now part of the input resistance to
v 2 1
the op-amp. We now write
We then have R + R = v(max)/i(max) = 0.1/ 5µ= 20 k(cid:3)
1 S s 1
R = 5R = 5(20) = 100 k(cid:3) A = -R / R = -5
2 1 v 2 1
Trade-offs:If the signal source has a finite output Since R = 1 k(cid:3), we then have R = 19 k(cid:3).
S 1
resistance and the desired output voltage is The feedback resistor is then
v = -0.5 sin (cid:2)t, the circuit must be redesigned. R = 5 (R + R ) = 5 (19k + 1k) = 100 k(cid:3)
o 2 1 S
Assume that the output resistance of the source is
R = 1 k(cid:3).
S (cid:3)(cid:1) (cid:3)(cid:2)
13.2.1) Basic Inverting Amplifier(Cont) 13.2.1) Basic Inverting Amplifier(Cont)
(cid:3)(cid:3) (cid:3)(cid:4)
13.2.1) Basic Inverting Amplifier(Cont) 13.2.2) Inverting Amplifier with a T-Network
•Assume that an inverting op-amp with A = -100 is to
v
be designed with R = R = 50 k(cid:4). The value of R
i 1 2
would have to be 5 M(cid:2), which is impractical.
•Therefore, a T-networkis used in the feedback loop
to overcome this problem as, shown in Figure 9.12.
Figure 9.12: Inverting op-amp with T-network
(cid:3)(cid:5) (cid:3)(cid:6)
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EEEB273 – Electronics Analysis & Design II
13.2.2) Inverting Amplifier with a T-Network (Cont) 13.2.2) Inverting Amplifier with a T-Network (Cont)
•At the input: •The sum of current at node v can be written as
X
v v v v -v
i = I =i (9.13) - X - X = X O (9.15)
1 R 2 R R R
1 2 4 3
•Can also write that or
vX =0-i2R2 =-vI(cid:4)(cid:4)(cid:5)(cid:6)RR12(cid:1)(cid:1)(cid:2)(cid:3) (9.14) vX(cid:4)(cid:4)(cid:5)(cid:6)R12 +R14 +R13(cid:1)(cid:1)(cid:2)(cid:3)= vRO3 (9.16)
•The sum of currents at node vXis •Using vXfrom Equation (9.14), can obtain
i2+i4 =i3 -v (cid:4)(cid:4)(cid:6)R2(cid:1)(cid:1)(cid:3)(cid:4)(cid:4)(cid:6) 1 + 1 + 1 (cid:1)(cid:1)(cid:3)= vO (9.17)
I(cid:5)R (cid:2)(cid:5)R R R (cid:2) R
(cid:3)(cid:7) 1 2 4 3 3 (cid:3)(cid:8)
13.2.2) Inverting Amplifier with a T-Network (Cont) 13.2.3) Effect of Finite Gain
•The closed-loop voltage gain A is therefore •A finite open-loop gainA (also called the finite
v od
v R (cid:6) R R (cid:3) diff-mode gain) affects closed-loop gain of an
A = O =- 2(cid:4)(cid:4)1+ 3 + 3(cid:1)(cid:1) (9.18) inverting amplifier. We will determine the magnitude
v v R (cid:5) R R (cid:2) of A required to approach the ideal case.
I 1 4 2 od
•Consider an inverting op-amp shown in Figure 9.13.
(cid:1)(cid:1)(cid:1)(cid:1)The advantage of using a T-network is that a
large gain can be obtained using reasonably
sized resistors.
•Self study Example 9.2
Figure 9.13: Equivalent circuit of the inverting op-amp with
(cid:3)(cid:9) a finite differential-mode gain. (cid:4)(cid:10)
13.2.3) Effect of Finite Gain(Cont) 13.2.3) Effect of Finite Gain(Cont)
•Assume an infinite input resistance at terminals •Combining Equations (9.21), (9.19), and (9.20),
(1) and (2) (cid:2)the input currents to op-amp are zero. and setting i = i, can obtain
1 2
•The current through R can be written as v v
1 v + O - O -v
i1= vIR-1v1 (9.19) i1= I R1Aod =i2 = AoRd2 O (9.22)
and the current through R is
2 •Solving for the closed-loop voltage gain:
i2 = v1R-2vO (9.20) Av =vvOI =-RR12 (cid:11)(cid:13)1+ 1 (cid:4)(cid:4)(cid:6)11+R2(cid:1)(cid:1)(cid:3)(cid:8)(cid:10) (9.23)
•The output voltage and voltage at terminal (1) are (cid:12) A (cid:5) R (cid:2)(cid:9)
od 1
vO =-Aodv1(cid:7)v1=-vO/Aod (9.21) (cid:4)(cid:1) (cid:1)(cid:1)(cid:1)(cid:1)When Aod(cid:3)(cid:3)(cid:3)(cid:3)(cid:1), the ideal Av= -(R2/ R1) (cid:4)(cid:2)
Lecturer: Dr Jamaludin Bin Omar 12-7
EEEB273 – Electronics Analysis & Design II
13.2.3) Effect of Finite Gain(Cont) 13.3) Summing Amplifier
•Self study Example 9.3 •The output voltage = sum of the input voltages.
•Figure 9.14 shows the summing amp circuit.
Figure 9.14: (a) Summing op-amp amplifier circuit
(cid:5)(cid:6)(cid:7)(cid:8) and (b) currents and voltages in the summing amp.
(cid:4)(cid:3) (cid:4)(cid:4)
13.3) Summing Amplifier(Cont) 13.3) Summing Amplifier(Cont)
•Assume A and Rapproach infinity. •Since v = v = 0 and the inverting terminal is at
od i I2 I3
virtual ground, the current i and i must be both 0.
2 3
•The output voltage due to each input voltage Current i does not flow through either R or R , but
1 2 3
acting alone can be determined from the use of the entire current must flow through the feedback
superposition theoremand the concept of resistor R , as indicated in Figure 9.14(b).
F
virtual ground. The total output is determined by
algebraically sum the output terms from each •The output voltage due to acting alone is
input.
(cid:6)R (cid:3)
v (v )=-iR =-(cid:4)(cid:4) F (cid:1)(cid:1)v (9.25)
•By setting v = v = 0, the current i is O I1 1 F (cid:5) R (cid:2) I1
I2 I3 1 1
v
i = I1
1 R (9.24)
1
(cid:4)(cid:5) (cid:4)(cid:6)
13.3) Summing Amplifier(Cont) 13.3) Summing Amplifier(Cont)
•Similarly, the output voltages due to v and v •The total output voltage then becomes
I2 I3
acting individually are
vO(vI2)=-i2RF =-(cid:4)(cid:4)(cid:5)(cid:6)RRF (cid:1)(cid:1)(cid:2)(cid:3)vI2 (9.26) vO =-(cid:4)(cid:4)(cid:5)(cid:6)RRF vI1+RRF vI2+ RRF vI3(cid:1)(cid:1)(cid:2)(cid:3) (9.29)
2 1 2 3
and (cid:6)R (cid:3)
v (v )=-i R =-(cid:4)(cid:4) F (cid:1)(cid:1)v (9.27) (cid:1)The output voltage is the sum of the three
O I3 3 F (cid:5) R (cid:2) I3 input voltages, with different weighting factors.
3
This circuit is therefore called the inverting
•The total output voltage is the algebraic sum of summing amplifier. The number of input terminals
the individual output voltages, or and input resistors can be changed to add more or
fewer voltages.
v =v (v )+v (v )+v (v ) (9.28)
O O I1 O I2 O I3 (cid:4)(cid:7) (cid:4)(cid:8)
Lecturer: Dr Jamaludin Bin Omar 12-8
EEEB273 – Electronics Analysis & Design II
13.3) Summing Amplifier(Cont) 13.3) Summing Amplifier(Cont)
•Special Case: If R = R = R = R, Example 9.4
1 2 3
R Objective: Design a summing to produce a
v =- F (v +v +v ) (9.30) specified output signal.
O R I1 I2 I3
Specifications:The output signal generated from a
(cid:1)The output voltage is the sum of the input BJT emitter follower is v = 5 -0.5 sin (cid:2)t(V) and
O1
voltages, with a single amplification factor. the effective output resistance is R = 50 (cid:3). Design
o
a summing amplifier to be connected to the emitter
•Instead of for summingamplifier, the op-amp can follower such that the output signal is v = 2 sin (cid:2)t
O
also be used to integrateand differentiate. These (V). Assume that the frequency (cid:2)is quite low, such
circuits are building blocks needed to perform that coupling capacitors are impractical.
analog computations (cid:1)original name of op-amp.
(cid:4)(cid:9) (cid:5)(cid:10)
13.3) Summing Amplifier(Cont) 13.3) Summing Amplifier(Cont)
Example 9.4 (Cont) Example 9.4 (Cont)
Choices: Standard resistor values with tolerances If we make R = R = 30 k(cid:3), then the effect of the
1 2
of 2 percent are to be used in the design. Assume 50 (cid:3)output resistance of the emitter follower is
an ideal op-amp is available. negligible. For a -0.5 V sinusoidal input signal and a
desired 2 V sinusoidal output signal, the summing
Solution:In this case, we need only two inputs to a amplifier gain must be
summing amplifier, as shown in Figure 9.14. One input to
the summing amplifier is the output of the emitter follower A = -R / R = 2 V/-0.5 V = -4
amplifier and the second input should be a dc voltage to v F 1
cancel the +5 V from the emitter-follower signal. If the gains For an input resistance R = 30 k(cid:3), the feedback
of each input to the summing amplifier are equal, then an 1
input of -5 V at the second input will cancel the +5 V from resistance must be RF= 120 k(cid:3).
the emitter-follower signal.
(cid:5)(cid:1) (cid:5)(cid:2)
13.3) Summing Amplifier(Cont) 13.4) Non-inverting Amplifier
Demo: my741Adder3 •Input signal v is applied directly to the non-
I
inverting terminal, while maintaining negative
Sign Inverter
feedback on inverting-terminal but connecting one
side of R to the ground. Refer to Figure 9.15.
1
Output Indicator
Input Voltage Summing Amp
Figure 9.15: Non-inverting op-amp circuit.
(cid:5)(cid:3) (cid:5)(cid:4)
Lecturer: Dr Jamaludin Bin Omar 12-9
EEEB273 – Electronics Analysis & Design II
13.4) Non-inverting Amplifier(Cont) 13.4) Non-inverting Amplifier(Cont)
•Negative feedback connection forces v = v (also The Closed-Loop Voltage Gain
1 2
known as virtual short)
(cid:1)A change in v will cause v to change in such a •Assume that no current enters the input terminals.
2 O
way that v is forced to track v Since v = v, then v = v, and current i and i are
1 2 1 2 1 I 1 2
(cid:1)The voltage difference between v and v is, for
1 2
practical purposes, zero. i = –v / R = –v / R (9.31)
1 1 1 I 1
i = (v –v ) / R = (v –v ) / R (9.32)
2 1 O 2 I O 2
•However, unlike a true short circuit, there is no
current flow directly from one terminal to the other. •Since i = i, then
1 2
The virtual short concept, i.e. v = v, is used as an –v / R = (v –v ) / R (9.33)
1 2 I 1 I O 2
ideal op-amp characteristic and this property is
used in the circuit analysis. •Therefore, the closed-loop voltage gain is
A = v / v = 1 + R / R (9.34)
(cid:5)(cid:5) v O I 2 1 (cid:5)(cid:6)
13.4) Non-inverting Amplifier(Cont) 13.4.1) Voltage Follower
•Characteristics of non-inverting amplifier: •For the non-inverting op-amp, when R = (cid:1)(open
1
(cid:2)Output is in phase with the input circuit) then A = 1. This is called a voltage-follower.
v
(cid:2)Gain is always greater than 1 The A is independent of R (except when R = (cid:1)), so
v 2 2
(cid:2)v is connected to non-inverting terminal and can set R = 0 to create a short circuit.
I 2
since input current is essentially zero (cid:2)input
impedance seen by the source is very large •Figure 9.17shows the voltage follower op-amp
(ideally infinite). circuit.
Figure 9.17: Voltage-follower op-amp circuit.
Figure 9.16: Equivalent circu(cid:1)it (cid:2)o(cid:3)(cid:4)f ideal non-inverting op-amp(cid:5)(cid:7) (cid:5)(cid:8)
13.4.1) Voltage Follower(Cont) 13.4.1) Voltage Follower(Cont)
•Voltage-follower: Buffer example: A voltage source with 100 k(cid:4) output
(cid:2)Output voltage follows input (A = 1). impedance driving a 1 k(cid:4) load impedance as shown
v
(cid:2)Input impedance (cid:2) (cid:1). in Figure 9.18(a).This situation may occur if the source
(cid:2)Output impedance = 0. is a transducer.
(cid:2)Used as impedance transformeror buffer
(impedance matching application):
(cid:1)If, for example, the output impedance of a
signal source is large, a voltage follower
inserted between the source and a load will
prevent loading effects, that is, it will act as a
buffer between the source and the load. Figure 9.18: (a) Source with a 100 k(cid:5) output resistance
driving a 1 k(cid:5) load and (b) source with a 100 k(cid:5) output
(cid:5)(cid:9) resistance, voltage follower, and 1 k(cid:5) load. (cid:6)(cid:10)
Lecturer: Dr Jamaludin Bin Omar 12-10
Description:Able to: • Develop the parameters and characteristics of the ideal op-amp and determine the analysis method of ideal op-amp circuits. • Analyze and
