HoLiSwap: Reducing Wire Energy in L1 Caches

0.75 MB·

by  Yatish Turakhia

HoLiSwap: Reducing Wire Energy in L1 Caches
YatishTurakhia1,SubhasisDas2,TorM.Aamodt3,andWilliamJ.
Dally4
7
1
0 1,2,4DepartmentofElectricalEngineering,StanfordUniversity
2 3DepartmentofElectricalandComputerEngineering,Universityof

n BritishColumbia
a
J 1,2,4{yatisht,subhasis,dally}@[email protected]

4
1

] Abstract
R
A ThispaperdescribesHoLiSwapamethodtoreduceL1cachewireenergy, a
significantfractionoftotalcacheenergy,byswappinghotlinestothecacheway
.
s nearest to the processor. We observe that (i) a small fraction (<3%) of cache
c
lines(hotlines)serveover60%oftheL1cacheaccessesand(ii)thedifferencein
[
wireenergybetweenthenearestandfarthestcachesubarraycanbeover6×. Our

1 methodexploitsthisdifferenceinwireenergytodynamicallyidentifyhotlinesand
v swapthemtothenearestphysicalwayinaset-associativeL1cache.Thisprovides
8
upto44%improvementinthewireenergy(1.82%savinginoverallsystemenergy)
7
withnoimpactonthecachemissrateand0.13%performancedrop.Wealsoshow
8
thatHoLiSwapcansimplifyway-prediction.
3
0
.
1 1 Introduction
0
7
Data movement across the memory hierarchy is increasingly becoming the dominant
1
: componentofenergy,bothinsmartphonesandsupercomputers. L1cachesexpendup
v
tohalfofthetotalmovementenergy[9,14]withroughlyequaldistributionininstruc-
i
X tion(L1-I)anddata(L1-D)cache.
r Inthispaper,weproposeHoLiSwap1,anorganizationthatmigrateshotcachelines
a to the nearest way of a set associative cache to minimize L1 cache wire energy with
negligibleimpactperformanceorarea.
HoLiSwap is motivated by two observations: First, certain cache lines are hot in
that they have a long cache lifetime and are frequently accessed during this lifetime.
Figure1showsthepercentageofaccessestohotlines(lineswith≥64hitsper128set
accesses)inL1cachesintheMobybenchmarks[8]. Thefigureshowsthatabout60%
ofallaccessesaretohotlines. Figure2showsthattheaveragehotlineremainsactive
for1,341setaccessesinL1-Dand1636setaccessesforL1-Icache(comparedto125
1UsedasanacronymforHotLineSwap.
1
L1-­‐D
  L1-­‐I

s
 100

e
hot
 lin 6800

o

s
 t 40

e
ss 20

e
c
ac 0

%
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 AVERAGE

Figure1:PercentageoftotalaccessestohotcachelinesinL1cache.
L1-­‐D
  L1-­‐I

6323
 16784

nes
  45500000

erage
 dura*on
 of
 hot
 li(#
 accesses)
 11223340505050500000000000000000

Av
Figure2:Averageduration(#accessestoitsset)ofhotcachelines.
accessesforanon-hotline). Onthesebenchmarksonly2.88%(2.45%)ofalllinesin
L1-D(L1-I)cachearehot.
Second,thewireenergyforthecachewaynearesttheprocessorcanbeasmuchas
6×lowerthanthewireenergyforthefarthestway. Thus,HoLiSwapmigratesthehot
cachelinestothenearercacheways,leveragingthisasymmetryinenergyconsumption
ofcacheways. AsweshowinSection4,thisstrategycanreduceL1cachewireenergy
consumptionby45%onanaveragefortheMobybenchmarksuite.
PriorworkonL1cacheenergyhasfocusedonminimizingSRAMaccessenergy.
Forinstance,way-prediction[15]speculativelypredictsandaccessesasinglewayfor
loadinstructionsinparallelwithtaglookup,resultinginloweraccessenergyforcor-
rect predictions. Filter cache [10], or L0 cache, adds a small cache between the pro-
cessor and the L1-cache to reduce L1-cache accesses. A number of techniques have
beenproposedtominimizethelatencyandenergyoverheadincurredonafiltercache
miss[3,12].
HoLiSwapissimilarinspirittoNuRAPID[6],whichrelocatesfrequentlyaccessed
cachelinestofastersubarraystoimproveperformanceoflast-levelNUCAcachesthat
employsequentiallook-upoftaganddataarrays.HoLiSwapimprovesuponNuRAPID
andNUCAbyfirstidentifyinghotlinesratherthanindiscriminatelyswappingthemost
recentlyusedlineaftereveryreference,leadingtolowerswappingoverheads,bothin
energyandperformance. WeshowinSection4thatfrequentswapsinL1cachecould
have high performance overhead. Also, L1 caches, in contrast to NUCA, have lower
latencyvariationbetweensubarraysandasubstantiallylargerperformanceimplication
2
epoch

 hit

HoLiSwap
  counters
  counters

0.123
 mm
  Controller

 W

 0

 W1

 W2

 W3

Subarray
  Subarray

 Set
 0

0.75
 mm
  (W8aKy

 BW
 1)
  4

 Swap
  (W8aKy

 BW
 3)

 Set
 1

  3

 Swa

 p

  Logarithmic

counters

 Set
 S

Subarray
  Subarray

(W8aKy

 BW
 0)
  (W8aKy

 BW
 2)

 1S2e7t

  2 “hot”

H
 >
 T

l
Control
 logic
  1 C
 =
 E

s
To
 way-­‐mul8plexer
  Cache
 lines
 in
 Set
 S

Figure3:OverviewofHoLiSwap.
with cache port blocking. HoLiSwap focuses on minimizing wire energy rather than
latency, and may use more complex lookup mechanisms, such as parallel lookup or
way-prediction,asdescribedinSection2.
2 Description
Figure3showstheorganizationof32KB,4-waysetassociativecacheusingHoLiSwap.
Eachwayisstoredinaseparate8KBsubarray. Todetecthotcachelines,thecontroller
maintainsanepochcounterC foreachsetsandahitcounterH foreachlinel. At
s l
thestartofeachepoch,allcountersarezero.C isincrementedoneachaccesstosand
s
H isincrementedoneachhittolinel. WhenC = E anewepochisstartedandall
l s
countersinthesetarezeroed. IfatanytimeH ≥T (whereT isathreshold),linelis
l
consideredhotandthehottestline(mostaccesses)isswappedtowayW ,thelowest
0
energyway. Theportsofthecacheareblockedwhentheswapisperformed,incurring
asmallperformancepenalty.
Toreducetheoverheadofmaintainingcounters,HoLiSwapuseslogarithmiccoun-
ters to store only the exponent (base 2) of H and C . At all times after the initial
l s
incrementfrom0to1,H =2e. OnahittolineltheexponenteofH isincremented
l l
withprobability1/2e.Thisrepresentationreducesthestorageoverheadby50%forthe
32KB4-waysetassociativecache(Section3)withlittledropinenergysaving(<2%)
comparedtoanexactcount.
HoLiSwap uses tri-state buffers to gate the data lines from the subarrays to the
processor based on the tag comparison to prevent the unselected lines from toggling
and dissipating energy. This gating is possible because latency to access the smaller
tagarrayislowerthanlatencytoaccessthelargerdatasubarrays(0.28nsfor2KBtag
arrayvs. 0.5nsfor8KBdatasubarray). Energyisstillconsumedcyclingthebitlines
oftheunselectedways.
The HoLiSwap can optionally employ way prediction [15] to avoid cycling the
unselected data subarrays — saving further energy, but with a small penalty in per-
formanceduetomispredictions. BecausetheHoLiSwapmigrationstrategyresultsin
mostaccessesbeingmadetoW ,alwayspredictingW providesareasonablyaccurate
0 0
way-predictor(asdescribedinSection4)atamuchlowerimplementationcost.
3
Table1: Totalenergy(inpJ)toaccessdifferentwaysofa4-way32KBL1cacheforsequential
andparallellookupmechanisms.Wireenergiesareindicatedinbrackets.
Way0 Way1 Way2 Way3
Sequential 5.7(1.6) 8.8(4.7) 10.9(6.8) 14.0(9.9)
Parallel 18.0(1.6) 21.1(4.7) 23.2(6.8) 26.3(9.9)
3 Methodology
We evaluate HoLiSwap using Gem5 [4] to simulate a 3-way out-of-order ARM pro-
cessor. Weuse10AndroidapplicationsfromtheMobybenchmarksuite[8]represent-
ing popular and emerging mobile workloads. We simulate 10M instructions (which
typicallycontains1-5Mload/storeinstructions)foreachbenchmarkfromcheckpoints
collectedatevery100Minstructions.
HSPICE is used to model the energy of a 32KB 4-way set associative L1 cache
withthephysicalorganizationshowninFigure3. Theoutputwiresfromthesubarrays
areroutedtotheway-multiplexernearwayW usingManhattanrouting. WeusePTM
0
wire and CMOS models [5] at the 22nm technology node. The model includes out-
putwireenergyandSRAMarrayaccessenergy(includingthedecoderandsenseamp
energy). Table1showsthetotalenergy(SRAM+wire)andthewireenergyrequired
toaccesseachwayoftheL1cacheforsequentialandparallellookup. Forsequential
lookup, we model the sum of array access energy and output wire energy of the ac-
cessedway(subarray). Forparallellookup,wemodelthesumofthearrayenergiesof
allwaysandtheoutputwireenergyoftherequiredway(sinceremainingoutputwires
havebeengated). Theparallellookupmechanismoffersanarrowerenergyrangefor
differentwayssincethetotalenergyislargelydominatedbytheparallelaccesstoall
ways. Thereisover6×variationinwireenergyfromclosesttofarthestway.
WesetE = 256andT = 128. Thesesettingsprovidedthemostgainexperimen-
tally (in terms of energy-delay product) over a sweep of E from 8 to 1024 accesses.
Energy improvements are relatively insensitive to T, but setting T to E/2 helps in
leveraginglogarithmiccountersandensuresthatatmostonelineishot. Thecacheis
blockedfor4-cyclesoneveryswapandtheenergyoverhead(2reads,2writes)foreach
swapisaccountedfor. Storingthe4-bitexponentialcounters(C andH )foreachset
s l
requires20-bitsofoverhead(insteadof40-bitsforexactcount). Wealsoaccountfor
theoverheadofthesimplecontroller.
We evaluate the benefits of HoLiSwap migration strategy on four different L1-D
cachedesigns:(1)SEQUENTIAL:tagsareaccessedfirstandthenonlytheselecteddata
arraysareaccessed—requiring3-cyclehitlatency;(2)PARALLEL:taganddataarrays
area accessed in parallel which reduces the hit latency to 2-cycles; (3) PREDICTION:
WeuseaPC-basedway-predictorbasedon[15]withoutHoLiSwapmigrationstrategy
as baseline and compare it with the static way-predictor having HoLiSwap migration
strategy as described in Section 2; (4) FILTER: This design uses a 1KB single cycle
directly-mappedL0cacheinadditiontothe32KBL1-Dcache. Theaccessenergyof
L0cacheis4.1pJ.
For PREDICTION, A 2-cycle hit latency is incurred for correctly predicted loads
4
HoLiSwap
 Speedup

 Speedup
 w/o
 HoLiSwap

 SRAM
 component

 Wire
 component

Figure4: Energy-Performance(normalizedto SEQUENTIAL)withandwithoutHoLiSwapmi-
grationinL1-Dcache.
SEQUENTIAL
  PARALLEL
  PREDICTION
  FILTER

45

%)
 40

n
 35

gs
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0

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 AVERAGE

Figure5:EnergysavingsinL1-DcachewiththeHoLiSwapmigrationpolicyforthefourcache
designs.
and an additional cycle for all stores and incorrectly predicted loads. Access energy
toeachcachelinecorrespondstothesequentialmechanismasonlyonewayisprobed
atatime. Wealsodisableselectivedirect-mappingsinceitaffectsthemissrateofthe
cache. Forperformancereasons,L1-IcachetypicallyusesPARALLELschemeonly.
4 Results
Figure 4 shows average performance and L1-D energy (normalized to SEQUENTIAL
withoutHoLiSwap)forthe4cachedesignswithandwithoutHoLiSwap. L1-Denergy
isfurtherbrokendowninSRAMarrayandwirecomponents. HoLiSwapsubstantially
reduces the L1-D cache wire energy for the first three designs. The gains, as a frac-
tion of the total L1-D cache energy, are largest for the SEQUENTIAL design (25.7%)
because it has the smallest SRAM array energy and most dominant wire component.
HoLiSwapsaves41.1%inthewirecomponentforSEQUENTIAL.HoLiSwapimproves
theenergyofPARALLELby12.1%(44.0%savinginwireenergycomponent)ofasub-
stantially larger baseline. HoLiSwap provided 22.1% energy improvement in L1-D
cache with 44.6% improvement in wire energy component in PREDICTION. FILTER
isindependentlymoreenergy-efficientthantheotherschemeswithHoLiSwap,asthe
5
L1-­‐D
 energy
  Execu1on
 Latency

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4
  8
  16
  32
  64
  128
  256
  512
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  E
Epoch
 length
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Figure6:NormalizedL1-Dcacheenergyandexecutionlatencyvs.epochlengthE.
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Accur 7800

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Figure7:Waypredictionaccuracyforthestaticway-predictorinHoLiSwap.
Way
 0
  Way
 1
  Way
 2
  Way
 3

ay
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H H H H H H H H H H H H H H H H H H H H
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Figure8:FractionofaccessesservedbyeachwaywithandwithoutHoLiSwapinMobybench-
marks.
6
L0cachefiltersoutmostreferencestohotlines,butithasaperformancelossof2.9%.
HoLiSwapwith FILTER provides4.74%energysavingsoverandabove FILTER. The
energy savings include the overheads of swapping and logarithmic counters, which
correspondto0.15%and0.62%oftheL1-Dcacheenergy,respectively. Thereissmall
performancedegradation(<0.13%)duetoblockingofcacheportsduringswapsinall
cachedesigns,exceptforPREDICTIONwhichhas0.3%performancedrop. Thisisdue
to higher average memory latency in HoLiSwap as a result of lower way-prediction
accuracy. Figure5showstheL1-DenergysavedbyHoLiSwaponeachbenchmarkfor
eachofthefourdesigns.
Figure 6 shows the sensitivity of L1-D cache energy and execution latency to
epochlengthEforSEQUENTIALwithHoLiSwap(normalizedtosameschemewithout
HoLiSwap). The threshold T was set to E/2. The energy savings range from 19.8%
(E=4) to 27.8% (E=64) relative to the baseline. Small values of E are impaired by
redundantswapswhilelargerE delaystheidentificationofhotlines,resultinginlost
opportunitiesforoptimization. TheperformancedegradationofHoLiSwapmovement
policy arising from blocking of cache port during cache line swap decreases with E,
from 7.78% for E=4 to 0.01% for E=1024. The energy overhead of swaps super-
sede the energy saved at small epoch lengths (E=4) and with a heavy performance
penalty,whichexplainswhyapolicylikeNuRAPIDcannotbeappliedtoL1-Dcache.
The overhead increases to 8.1% when L1-I cache also uses HoLiSwap. At the same
time,theout-of-orderexecutionoftheprocessorhelpsinhidingtheadditionalmemory
latency during swaps to a great extent. Our choice of E=256 shows the best energy-
delayproduct,alsotakingprocessorandDRAMenergyintoaccount,withanaverage
of0.13%performanceloss.
Figure7showsthewaypredictionaccuracyfortheproposedstaticwayprediction,
whichalwayspredictsW ,provides67.8%accuracyonanaverage. Ourbaselineway-
0
predictor based on [15] had an accuracy of 81.8% but with a higher implementation
cost. Evenwithloweraccuracy,staticway-predictionalongwithHoLiSwapmigration
strategyprovides25.7%energyimprovementoverbaseline.
Energyimprovementsforvariousworkloadsareroughlycorrelatedwiththefrac-
tion of accesses to hot lines in Figure 1, but they also depend on the distribution of
accesses to each way in absence of HoLiSwap migration policy. Figure 8 shows the
fraction of accesses served by each way with and without HoliSwap in L1-D cache.
Largestenergyimprovementswereobservedincaseof360buybenchmark,sincemost
oftheaccessesweremadetotheleastenergy-efficientway(W )ofthecache(nearly
3
all hot lines were placed in this way) by the replacement policy and relocated to the
mostenergy-efficientway(W )byHoLiSwap.
0
WealsoevaluatedHoLiSwapfordifferentL1-DcachesizesforSEQUENTIAL.The
associativityofthecache(4-way)andthesizesofdatasubarrays(8KB)werekeptun-
changed. We changed the physical organisation in figure 3 to 2(rows)×1(columns)
and 2×4 arrangement of subarrays for 16KB and 64KB cache, respectively. The en-
ergyrangeforaccessingdifferentwaysdecreasedfrom2.45×in32KBcacheto1.54×
in 16KB cache and with that, the energy savings from HoLiSwap also dropped from
27.8% in 32KB cache to 9.5% in 16KB cache. For 64KB cache, which had 3.16×
energyvariationindifferentways,theenergysavingsincreasedto34.3%. Theperfor-
mancein16KBcachewas0.71%lowerthanthatwith32KBcache,while64KBcache
7
heap
  library
  stack
  kernel

100%

s
  90%

se 80%

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e 70%

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Ac 60%

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  50%

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  40%

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Figure9:FractionofreferencesservedfromdifferentaddressregionsinMobybenchmarks.
improvedtheperformanceby1.2%.
HoLiSwap,whenappliedtoL1-Icache,resultsin11.6%energysavingwithPAR-
ALLEL scheme. Since performance is more sensitive to the L1-I cache latency, other
lookupschemes,suchasSEQUENTIAL(3.6%performancedrop),arerarelyused.
UsingMcPAT[13]on22nmARMA9processor,weobservedthatthe32KBL1-I
cachewithPARALLELcorrespondsto8.6%ofthememorysubsystemenergy(caches+
DRAM).The32KBL1-Dcacheconstitutes14.7%and6.9%ofthememorysubsystem
energy using PARALLEL and SEQUENTIAL, respectively. HoLiSwap can, therefore,
save up to 3.42% of the total memory subsystem energy and 1.82% of total system
energy(processor+DRAM)at0.13%combinedperformanceloss.
5 Related Work
LeeandTyson[11]observedthatinSpecCPU2000benchmarks[7],amajorityofhot
linesbelongedtothestackregionofthevirtualaddressspace(usingaslightlydifferent
definition of hot). By using a small stack cache in addition to a large heap cache
(L1-D cache), they achieved a power reduction of over 50%. However, the proposed
region-based caching approach is not generally applicable to all workloads, such as
mobile applications in Android. Figure 9 shows the relative distribution of accesses
intheAndroidworkloadsfromMobybenchmarksuitebelongingtotheheap, shared
library,stackandkernelregions. Sinceanumberofobjectsgetcreateddynamicallyin
theheapspaceintheseworkloadsandduetothepresenceoffrequentsystemlibrary
calls,stackregiononlycorrespondstoonlyasmallpercentageofthetotalL1-Dcache
accesses.Amajorityofaccessesbelongtotheheapandsystemlibraryregions,making
region-basedcachingapproachineffective. HoLiSwapovercomesthisshortcomingby
notdifferentiatingbetweenthehotlinesbelongingtothedifferentregionsofthecache.
Besides, unlike region-based caching, HoLiSwap has no impact on the overall miss
rateofthecacheasitdoesnotstaticallypartitionthecache.
HoLiSwapwithPREDICTIONissimilartohash-rehash[1],column-associative[2]
andmulti-columncaches[16],inwhichlinesareswappedtoapreferredway(W )that
0
isalsoaccessedfirst(oftentoreducelatencyoftaglookup),butthemaindistinctionof
8
HoLiSwapisthatitmovesonlythehotlinestoW ateveryepochinsteadofthemost
0
recentlyusedlineaftereveryreference.
6 Conclusion
In this paper we have described HoLiSwap which reduces L1 cache wire energy by
swappinghotcachelinestothecachewaynearesttheprocessor. Thisprovidesupto
44%improvementinthewireenergywithnoimpactonthecachemissrate.HoLiSwap
canbeemployedwithsequentialorparallelcacheaccessandcanbecombinedwithan
L0 filter cache or cache way prediction. When combined with cache way prediction,
HoLiSwapsimplifiesthepredictionbyallowingthenearestwayW toalwaysbepre-
0
dicted.
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