Higher Radix Floating-Point Representations for FPGA-Based Arithmetic

105 Pages·2017·0.82 MB·English

BBrriigghhaamm YYoouunngg UUnniivveerrssiittyy
BBYYUU SScchhoollaarrssAArrcchhiivvee
Theses and Dissertations
2005-04-22
HHiigghheerr RRaaddiixx FFllooaattiinngg--PPooiinntt RReepprreesseennttaattiioonnss ffoorr FFPPGGAA--BBaasseedd
AArriitthhmmeettiicc
Bryan Christopher Catanzaro
Brigham Young University - Provo
Follow this and additional works at: https://scholarsarchive.byu.edu/etd
Part of the Electrical and Computer Engineering Commons
BBYYUU SScchhoollaarrssAArrcchhiivvee CCiittaattiioonn
Catanzaro, Bryan Christopher, "Higher Radix Floating-Point Representations for FPGA-Based Arithmetic"
(2005). Theses and Dissertations. 311.
https://scholarsarchive.byu.edu/etd/311
This Thesis is brought to you for free and open access by BYU ScholarsArchive. It has been accepted for inclusion
in Theses and Dissertations by an authorized administrator of BYU ScholarsArchive. For more information, please
contact [email protected], [email protected].
HIGHER RADIX FLOATING-POINT REPRESENTATIONS FOR
FPGA-BASED ARITHMETIC
by
Bryan C. Catanzaro
A thesis submitted to the faculty of
Brigham Young University
in partial fulfillment of the requirements for the degree of
Master of Science
Department of Electrical and Computer Engineering
Brigham Young University
August 2005

Copyright (cid:13)c 2005 Bryan C. Catanzaro
All Rights Reserved

BRIGHAM YOUNG UNIVERSITY
GRADUATE COMMITTEE APPROVAL
of a thesis submitted by
Bryan C. Catanzaro
This thesis has been read by each member of the following graduate committee and
by majority vote has been found to be satisfactory.
Date Brent E. Nelson, Chair
Date Michael J. Wirthlin
Date Doran K. Wilde

BRIGHAM YOUNG UNIVERSITY
As chair of the candidate’s graduate committee, I have read the thesis of Bryan C.
Catanzaro in its final form and have found that (1) its format, citations, and bibli-
ographical style are consistent and acceptable and fulfill university and department
style requirements; (2) its illustrative materials including figures, tables, and charts
are in place; and (3) the final manuscript is satisfactory to the graduate committee
and is ready for submission to the university library.
Date Brent E. Nelson
Chair, Graduate Committee
Accepted for the Department
Michael A. Jensen
Graduate Coordinator
Accepted for the College
Douglas M. Chabries
Dean, Ira A. Fulton College
of Engineering and Technology

ABSTRACT
HIGHER RADIX FLOATING-POINT REPRESENTATIONS FOR
FPGA-BASED ARITHMETIC
Bryan C. Catanzaro
Department of Electrical and Computer Engineering
Master of Science
Field Programmable Gate Arrays (FPGAs) are increasingly being used for
high-throughput floating-point computation. It is forecasted that by 2009, FPGAs
will provide an order of magnitude greater sustained floating-point throughput than
conventional processors [1]. FPGA implementations of floating-point operators have
historically been designed to use binary floating-point representations, as do general
purpose processors. Binary representations were chosen as the standard over three
decades ago because they provide maximal numerical accuracy per bit of floating-
point data. However, the unique nature of FPGA-based computation makes numeri-
cal accuracy per unit of FPGA resources a more important measure of the usefulness
of a given floating-point representation.
Fromthisviewpoint, higherradixfloating-pointrepresentationsarewellsuited
toFPGA-basedcomputations,especiallyhighprecisioncalculationswhichrequirethe
support of denormalized numbers. This work shows that higher radix representations
lead to more efficient use of FPGA resources. For example, a hexadecimal floating-
point adder provides a 30% lower Area-Time product than its binary counterpart,