High-Voltage class-D power amplifiers: design and optimization

118 Pages·2015·1.86 MB·English

HIGH-VOLTAGE CLASS-D POWER AMPLIFIERS:
DESIGN AND OPTIMIZATION

Haifeng Ma

HIGH-VOLTAGE CLASS-D POWER AMPLIFIERS:
DESIGN AND OPTIMIZATION

Haifeng Ma
The Graduation Committee:
Chairman and secretary:
Prof. dr. P.M.G. Apers University of Twente
Promotor:
Prof. dr. ir. B. Nauta University of Twente
Assistant promotor:
Dr. ir. R.A.R. van der Zee University of Twente
Referee:
Dr. ir. M. Berkhout NXP Nijmegen
Members:
Prof. dr. ir. A.H.M. van Roermund Eindhoven University of Technology
Prof. dr. ir. C.H. Slump University of Twente
Prof. dr. ir. M. Steyaert KU Leuven
Prof. ir. A.J.M. van Tuijl University of Twente

This research is supported by the Dutch Technology
Foundation STW, which is part of the Netherlands
Organisation for Scientific Research (NWO) and partly
funded by the Ministry of Economic Affairs (project
number 10602).

CTIT Ph.D. Thesis Series No. 15-358
Centre for Telematics and Information Technology
P.O. Box 217, 7500 AE
Enschede, The Netherlands.

Title: High-Voltage Class-D Power Amplifiers: Design and Optimization
ISSN: 1381-3617 (CTIT Ph.D. Thesis Series No. 15-358)
ISBN: : 978-90-365-3870-1
DOI: 10.3990/1.9789036538701
http://dx.doi.org/10.3990/1.9789036538701

Copyright © 2015 by Haifeng Ma, Enschede, The Netherlands
HIGH-VOLTAGE CLASS-D POWER AMPLIFIERS:
DESIGN AND OPTIMIZATION

DISSERTATION

to obtain
the degree of doctor at the University of Twente,
on the authority of the rector magnificus,
prof.dr. H. Brinksma,
on account of the decision of the graduation committee,
to be publicly defended
on Friday 12 June 2015 at 16:45

by

Haifeng Ma
born on 24 October 1985
in Jiangsu, China
This dissertation has been approved by:
Promotor: Prof. dr. ir. B. Nauta

Assistant Promotor: Dr. ir. R.A.R. van der Zee
To My Family

ABSTRACT

Nowadays transducers are ubiquitous as interfaces between the increasingly digital world
and the real physical world. The same holds for the power amplifiers driving them. This thesis
focuses on the design and optimization of high-voltage class-D amplifiers, which are used for
driving capacitive piezoelectric actuator loads in active vibration/noise control applications.
The main objective is to further enhance class-D power efficiency compared to existing class-
D designs.
To gain insight in class D power efficiency, a detailed analysis of high-voltage class-D
dissipation sources is performed and a dissipation model including all the major dissipation
sources is developed. The analysis shows that switching loss is a potential dominating
dissipation source in high-voltage applications, while its contribution can be minimized by
fast switching to eliminate V-I overlap losses. Moreover, it is shown that when varying the
class-D switching frequency, a minimum total dissipation exists, with the optimal switching
frequency depending on the output power. Furthermore, idle loss reduction by increasing the
switching frequency and inserting a dead time to the power stage is backed by the analysis.
Following the analysis, a fast-switching power stage is designed to aim for switching loss
minimization. This output stage design features immunity to the on-chip supply bounce,
realized by internally regulated floating supplies, variable driving strength for the gate driver,
and an efficient 2-step level shifter design. Fast switching transitions and low switching loss
are achieved with 94% peak efficiency for the complete class-D power stage in the realized
chip. In addition, gate driver sizing procedures for the class-D output stage are discussed,
showing that the variable gate driving strength can greatly improve efficiency when on-chip
supply bounce is the limiting factor.
Also based on the dissipation analysis, this thesis describes the design of an efficiency-
improved high-voltage class-D power amplifier. The amplifier adaptively regulates its
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switching frequency for optimal power efficiency across the full output power range. This is
based on detecting the switching output node voltage level at the turn-on transition of the
power switches. For the final chip prototype, the amplifier achieves 93% efficiency at 45W
output power, >80% power efficiency down to 4.5W output power and >49% efficiency down
to 0.45W output power.
Finally, for the aim of idle loss reduction, the linearity degradation of dead time insertion
and switching frequency increase is discussed in this thesis. To cope with this linearity
degradation, both open-loop and closed-loop error correction techniques are explored and it
is further shown that a higher-order loop filter combined with uniform sampling once per
switching cycle is potentially a suitable choice for closed-loop fixed-carrier class-D
implementations.

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