High Performance Non-Volatile Ternary Content Addressable Memory Design UsingMemristor ...

326 Pages·2017·2.13 MB·English

A Thesis in the partial fulfillment of the degree of
Masters of Science in
Electrical and Electronic Engineering

on

High Performance Non-Volatile
Ternary Content Addressable Memory Design
UsingMemristor-MOSFET Hybrid Architecture.

Submitted by

Farhana Parveen

Student ID. - 1014062244

Supervisedby

Dr. A. B. M. Harun-urRashid
Professor

Department of Electrical and Electronic Engineering
Bangladesh University of Engineering and Technology

December, 2016
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Author’s Declaration

I hereby declare that this thesis or any part of it has not been submitted elsewhere for the award
of any degree or diploma.

Farhana Parveen
December, 2016

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Abstract

Content Addressable Memory (CAM)accesses a stored data word based on its contents,
compares it with a search word and returns the address of the matched word. This comparison
and search operationsare done within the memorycell, without the assistance of Arithmetic Logic
Unit (ALU). Due to this in-memory search facility, CAM can be a crucial circuit element in
high-speed search engine, data base engine, artificial neural network for neuromorphic
computingand other applications for Internet of Things (IoT).Ternary Content Addressable
Memory (TCAM) can store and compare two bits of data in a single cell.Thus it can be used to
represent three states- High, Low and Don‟t Care. This third state can provide Masking, which
allows to search a portion of the word, instead of the whole word. Thus TCAMadds more
flexibility in the search operation, and hence, has huge demand in IoT applications. In this work,
we have proposed a non-volatile memristor-MOSFET hybrid architecture of TCAM cell. The
memristormodel used in this work is calibrated to match the physical characterization data of
practical Ta-O based memristor. Furthermore, two match-line segmentation schemes- selective
charging and pipelining are implemented in order to make the proposed TCAM cell work more
reliably and efficiently in larger memory arrays. Finally, corner simulations are done to verify
the robustness of the proposed design against process, voltage and temperature variation. The
results obtained from the simulation are compared with that of conventional transistor based
TCAM design and other memristor-MOSFET hybrid TCAM designs. The comparison shows
significant performance improvement based on the following criteria- search time, search energy
(per bit) and voltage margin. This reduces the overall search time up to 83%, energy per bit up to
77.81% during match and 99.45% during mismatch; and increases voltage margin up to 81.19%
than the conventional TCAM design with MOSFETs. In other words, the proposed design shows
significant performance improvement with respect to conventional TCAM designs and more
practical applicability than other memristor-MOSFET hybrid TCAM designs. Therefore, this
design can be a better alternative for future memory, computing and IoT applications.

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Acknowledgements

At first I would like to express my earnest gratitude to my Creator, without whose grace and
blessings it would not have been possible on my part to complete this work. It is our Almighty,
who lets us do what we want and try to do, and helps us achieve what is good for us.

I would like to thank mysupervisor, Dr. A.B.M. Harun-Ur-Rashid sir, for his strong and generous
support for the completion of this work.He not only helped me know and explore in the realm of
knowledge related to my study and research, but also taught me how to survive in this world with
a broader sense of humanity and firmness.His vast knowledge in the field of VLSI design, has
established a rigid platform for research on VLSI in our country- Bangladesh. He undoubtedly
deserves the honor for letting students know and learn the usage and applicability of VLSI
design tools for their future research in home and abroad. This definitely helps the students to a
significant extant in every step of their future educational and professional life. I feel myself
blessed to be one of his students, who got the opportunity of working under his supervision and
stepping into the vast arena of research. From the beginning to the end of my thesis works,he
helped me his best to know and learn significant details of my work. He showed me the right
path to success and led me toward the successful completion of the work within the allocated
time span. Without his help and support, it was impossible for me to complete and submit my
work within the time. I do appreciate his tremendous contribution in this work from the deepest
core my heart.

My enormous thankfulness also goes to my dearest parents who gave me full freedom to carry on
my studies and research. Their love and moral support always inspired me to dream big and try
my best to fulfill that dream. At times of depression they never tire of showing the light of hope
to me. They are always there to motivate me when I need. Without their care and support it
would not be an easy job to complete my work.

Farhana Parveen
December, 2016

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To my Parents

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Table of Contents

Chapter-1 Introduction .................................................................................................................................. 1
1.1. Introduction ................................................................................................................................... 1
1.2. Motivation for this work ............................................................................................................... 2
1.3. Thesis Organisation ...................................................................................................................... 3
Chapter-2 Memristor ................................................................................................................................... 4
Chapter-3 Advancement in TCAM Design ................................................................................................ 14
3.1. Content Addressable Memory (CAM) ........................................................................................ 14
3.2. Ternary Content Addressable Memory (TCAM) ........................................................................ 14
3.2.1. Conventional 16T TCAM cell ............................................................................................ 15
3.2.2. 12 Transistor 2 Memristor TCAM Cell .............................................................................. 17
3.2.3. 8 Transistor 4 Memristor TCAM cell ................................................................................. 20
3.2.4. Proposed modifications in 8 Transistor 4 Memristor Structure .......................................... 21
Chapter-4 TCAM Array .............................................................................................................................. 29
4.1. Memory Array ............................................................................................................................ 29
4.2. Sense Amplifier .......................................................................................................................... 29
4.3. Charging ...................................................................................................................................... 30
4.4. Resetting ..................................................................................................................................... 31
4.5. Entire Row .................................................................................................................................. 32
4.6. Match-line Segmentation ............................................................................................................ 32
Chapter-5 .................................................................................................................................................... 34
Match-line Segmentation: Selective Charging ........................................................................................... 34
5.1. Array Operation .......................................................................................................................... 34
5.2. Simulation Results ...................................................................................................................... 36
5.2.1. Write Operation................................................................................................................... 36
5.2.2. Search Operation ................................................................................................................. 38
Chapter-6 .................................................................................................................................................... 40
Match-line Segmentation: Pipelining.......................................................................................................... 40
6.1. Array Operation .......................................................................................................................... 40
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6.2. Simulation Results ...................................................................................................................... 42
6.2.1. Write Operation................................................................................................................... 42
6.2.2. Search Operation ................................................................................................................. 44
Chapter-7 Result Analysis .......................................................................................................................... 46
7.1. Corner Simulation ....................................................................................................................... 46
7.2. Simulation Results for Selective Charging Scheme .................................................................... 46
7.3. Simulation Results for Pipelining Scheme .................................................................................. 48
7.4. Comparison among different TCAM designs ............................................................................. 50
7.4.1. Comparison in terms of speed ............................................................................................. 51
7.4.2. Comparison in terms of Energy per bit ............................................................................... 51
7.4.3. Comparison in terms of Voltage Margin ............................................................................ 51
7.4.4. Comparison Between Selective Charging and Pipelining Schemes ................................... 52
Chapter-8 Conclusion and Future Works .................................................................................................... 53
8.1. Conclusion .................................................................................................................................. 53
8.2. Future Works .............................................................................................................................. 54
References ................................................................................................................................................... 55
Appendix A ................................................................................................................................................. 57
A.1. PSpice netlist for Figures 2.8, 2.9 and 2.10 ................................................................................ 57
A.2. PSpice netlist for Figures 5.4, 5.5 and 5.6 and Table 7.2 ............................................................ 59
A.3. PSpice netlist for Figures 6.4, 6.5 and 6.6 ................................................................................ 102
A.4. PSpice netlist for Table 7.3 ....................................................................................................... 146
A.5. PSpice netlist for Table 7.4 ....................................................................................................... 188
A.6. PSpice netlist for Table 7.7 ....................................................................................................... 230
A.7. PSpice netlist for Table 7.8 ....................................................................................................... 273

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List of Figures

Figure 2.1 Relations between four variables of basic electrical circuit theory ............................................. 5
Figure 2.2 Interrelation among the four variables of basic electrical circuit theory ..................................... 5
Figure 2.3 A single memristor‟s functionalism ............................................................................................ 7
Figure 2.4 Electrical performance of tantalum oxide based memristors. Repeatable high speed switching
under 2 ns measured in real-time for ON and OFF switching with a less than 2 V pulse (showing ten
voltage–time curves for each) Upper right inset shows the reproducibility of the resistance values for the
first ten ON and OFF pulses . ........................................................................................................................ 8
Figure 2.5 Diagrams that describe the functionality of the SPICE model where the circuit in (a)
determines the I-V relationship of the memristor model and (b) shows how the value of the state variable
is determined. .............................................................................................................................................. 10
Figure 2.6PSpice subcircuit for the generalized memristor device model proposed in [8] ........................ 11
Figure 2.7 Circuit used for PSpice simulations ........................................................................................... 12
Figure 2.8Pspice simulation results for a single memristor connected to a sinusoidal voltage source ....... 12
Figure 2.9Hysteresis in a single memristor for a complete input cycle ...................................................... 13
Figure 2.10Hysteresis in a single memristor for 10 consecutive input cycles ............................................ 13
Figure 3.1(a) Global Masking (b) Local Masking ..................................................................................... 14
Figure 3.2Conventional 16T NOR type TCAM cell .................................................................................. 15
Figure 3.3 12T2M Hybrid structure of TCAM cell .................................................................................. 18
Figure 3.4 (a) Circuit when SS=0, RS=1 (b) Circuit when SS=1, RS=0. ................................................... 19
Figure 3.5 8T4M Hybrid structure of TCAM cell .................................................................................... 21
Figure 3.6Modified 8T4M hybrid structure of TCAM cell ........................................................................ 22
Figure 3.7 8T4M Cell during Search Operation ........................................................................................ 23
Figure 3.8 Direction of Current Flow for Writing (a) Logic „1‟, (b) Logic „0‟ .......................................... 27
Figure 3.9 Search Operation: (a) „Low‟ voltage level is produced at DT1 (or DT2) in case logic „1‟ was
written in Mem1 (or Mem2), (b) „High‟ voltage level is produced at DT1 (or DT2) in case logic „0‟ was
written in Mem1 (or Mem2) ....................................................................................................................... 28
Figure 4.1. An N×N TCAM Array ............................................................................................................ 29
Figure 4.2. Sense Amplifier ....................................................................................................................... 30
Figure 4.3 Charging Circuitry: (a) Inefficient charging, (b) Efficient charging, but requires ML reset ..... 31
Figure 4.4 Resetting Circuitry ..................................................................................................................... 32
Figure 4.5 An entire row with 64 TCAM cells (128 bits) ........................................................................... 32
Figure 5.1 Match-line segmentation: Selective Charging- (a) 1st segment (b) 2nd segment (c) 3rd
segment (d) 4th segment .............................................................................................................................. 35
Figure 5.2 An entire row of the Selective Charging scheme ...................................................................... 35
Figure 5.3 NOR Gate driving the Sense amplifier ...................................................................................... 36
Figure 5.4 Write Operation ......................................................................................................................... 37
Figure 5.5 Search Operation for Matching Condition (Selective Charging Scheme) ................................. 38
Figure 5.6 Search Operation for Mismatching Condition (Selective Charging Scheme) – 1- bit mismatch
in 1st segment ............................................................................................................................................. 39
Figure 6.1 Match-line segmentation: Pipelining- (a) 1st segment (b) 2nd segment (c) 3rd segment (d) 4th
segment ....................................................................................................................................................... 41
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Figure 6.2 Match-line segmentation: Pipelining ......................................................................................... 41
Figure 6.3 NOR Gate driving the Sense amplifier ...................................................................................... 42
Figure 6.4 Write Operation ......................................................................................................................... 43
Figure 6.5 Search Operation for Matching Condition (Pipelining Scheme) ............................................... 44
Figure 6.6 Search Operation for Mismatching Condition (Pipelining Scheme) – 1- bit mismatch in 1st
segment ....................................................................................................................................................... 45

List of Tables

Table 3.1 Representation of three states using two bits 24
Table 3.2 Match and Mismatch conditions during search operation 25
Table 3.3 Masking Conditions 25
Table 3.4 Forbidden States 26
Table 5.1 Results of Write Operation 38
Table 5.2 Results of Search Operation with Selective Charging 39
Table 6.1 Results of Write Operation 44
Table 6.2 Results of Search Operation with Pipelining 45
Table 7.1 Specifications for Corner Simulation 46
Table 7.2 Search Time and Energy per bit for Selective Charging in Normal Mode 46
Table 7.3 Search Time and Energy per bit for Selective Charging in Fast Mode 47
Table 7.4 Search Time and Energy per bit for Selective Charging in Slow Mode 47
Table 7.5 Voltage Margin for Selective Charging Scheme 48
Table 7.6 Search Time and Energy per bit for Pipelining in Normal Mode 48
Table 7.7 Search Time and Energy per bit for Pipelining in Fast Mode 49
Table 7.8 Search Time and Energy per bit for Pipelining in Slow Mode 49
Table 7.9 Voltage Margin for Pipelining Scheme 49
Table 7.10 Comparison Among Different TCAM Designs 50

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