high performance analog circuit design using floating-gate techniques

124 Pages·2007·1.48 MB·English

HIGH PERFORMANCE ANALOG CIRCUIT DESIGN
USING FLOATING-GATE TECHNIQUES
A Thesis
Presented to
The Academic Faculty
by
Guillermo J. Serrano
In Partial Fulfillment
of the Requirements for the Degree
Doctor of Philosophy in the
School of Electrical and Computer Engineering
Georgia Institute of Technology
December 2007
Copyright (cid:176)c 2007 by Guillermo J. Serrano
HIGH PERFORMANCE ANALOG CIRCUIT DESIGN
USING FLOATING-GATE TECHNIQUES
Approved by:
Dr. Kevin Kornegay, Dr. Jennifer Michaels
Committee Chair School of Electrical and Computer
School of Electrical and Computer Engineering
Engineering Georgia Institute of Technology
Georgia Institute of Technology
Dr. Paul Hasler, Advisor Dr. Levent Degertekin
School of Electrical and Computer School of Mechanical Engineering
Engineering Georgia Institute of Technology
Georgia Institute of Technology
Dr. David Anderson Date Approved: 26 July 2007
School of Electrical and Computer
Engineering
Georgia Institute of Technology
To my parents,
Muneca y Luis,
and to my brothers,
Luis y Pablo
iii
ACKNOWLEDGEMENTS
I would like to thank Dr. Paul Hasler for his guidance and numerous stimulating
conversations during the course of my doctoral studies. Thanks are due to the mem-
bers of my committee for all the insightful comments that have helped shape this
dissertation.
Manythanksto membersof ICElabfor puttingupwith meduringmysixyearsat
GaTech. VenkateshSrinivasanandAbhishekBandyopadyayrequireaspecialmention
for being both a great friend and an excellent work partner. It has been a pleasure
working with you!
Finally I want to thank my parents Muneca and Luis, and my brothers Luis and
Pablo. This work would not have been possible without their love, support, and
encouragement.
iv
TABLE OF CONTENTS
DEDICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
ACKNOWLEDGEMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
LIST OF TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii
LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix
SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiv
I MISMATCH: AN ANALOG CIRCUIT PERFORMANCE LIMITATION 1
1.1 Device Mismatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 MOS Matching Models . . . . . . . . . . . . . . . . . . . . 2
1.1.2 Bipolar Matching Models . . . . . . . . . . . . . . . . . . . 3
1.2 Getting Around Mismatch . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Effect of Device Mismatches on Circuit Performance . . . . . . . . 5
1.3.1 Mismatch in Amplifiers . . . . . . . . . . . . . . . . . . . . 5
1.3.2 Mismatch in Voltage References . . . . . . . . . . . . . . . . 6
1.3.3 Mismatch in Current References . . . . . . . . . . . . . . . 7
1.3.4 Mismatch in Current-Steering Digital-to-Analog Converters 9
II A PROGRAMMABLE ANALOG MEMORY . . . . . . . . . . . . . . . 10
2.1 Floating-Gate Transistor: An Analog Memory . . . . . . . . . . . . 10
2.1.1 Circuit Description . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.2 Analytical Description . . . . . . . . . . . . . . . . . . . . . 11
2.2 Charge Modification Mechanisms . . . . . . . . . . . . . . . . . . . 13
2.2.1 Fowler-Nordheim Tunneling . . . . . . . . . . . . . . . . . . 13
2.2.2 Hot-Electron Injection . . . . . . . . . . . . . . . . . . . . . 14
2.3 Programming Precision . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3.1 Weak Inversion . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3.2 Strong Inversion . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . 17
v
2.4 Automated Rapid Programming of Floating-Gates . . . . . . . . . 19
2.4.1 Array Characterization . . . . . . . . . . . . . . . . . . . . 20
2.4.2 Mathematical Model . . . . . . . . . . . . . . . . . . . . . . 21
2.4.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . 24
2.5 Charge Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.5.1 Long Term Charge Loss . . . . . . . . . . . . . . . . . . . . 29
2.5.2 Radiation Effects . . . . . . . . . . . . . . . . . . . . . . . . 32
2.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
III A PRECISION CMOS AMPLIFIER . . . . . . . . . . . . . . . . . . . . 34
3.1 Previous Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.2 Proposed Offset Voltage Compensation . . . . . . . . . . . . . . . 36
3.2.1 Amplifier Architecture . . . . . . . . . . . . . . . . . . . . . 37
3.2.2 Input Referred Offset Voltage Cancelation . . . . . . . . . . 37
3.2.3 Offset Voltage Temperature Sensitivity . . . . . . . . . . . . 38
3.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
IV A PROGRAMMABLE LOW TC CMOS VOLTAGE REFERENCE . . . 46
4.1 Previous Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.2 Proposed Voltage Reference . . . . . . . . . . . . . . . . . . . . . . 47
4.3 Reference Architecture #1 . . . . . . . . . . . . . . . . . . . . . . . 48
4.3.1 Reference Temperature Sensitivity . . . . . . . . . . . . . . 50
4.3.2 Reference Minimum Power Supply . . . . . . . . . . . . . . 51
4.3.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . 51
4.4 Reference Architecture #2 . . . . . . . . . . . . . . . . . . . . . . . 57
4.4.1 Reference Temperature Sensitivity . . . . . . . . . . . . . . 58
4.4.2 Reference Minimum Power Supply . . . . . . . . . . . . . . 58
4.4.3 Experimental Results . . . . . . . . . . . . . . . . . . . . . 58
4.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
vi
V A PROGRAMMABLE LOW TC CMOS CURRENT REFERENCE . . 63
5.1 Previous Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.2 A Programmable Current Reference . . . . . . . . . . . . . . . . . 64
5.3 A Temperature Compensated Resistor . . . . . . . . . . . . . . . . 66
5.3.1 A Programmable Resistor . . . . . . . . . . . . . . . . . . . 67
5.3.2 A Low TC Resistor . . . . . . . . . . . . . . . . . . . . . . . 70
5.4 Proposed Current Reference . . . . . . . . . . . . . . . . . . . . . . 71
5.5 Charge Modification . . . . . . . . . . . . . . . . . . . . . . . . . . 71
5.6 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
VI A V COMPENSATED DIGITAL-TO-ANALOG CONVERTER . . . 83
TH
6.1 Previous Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.2 DAC Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.2.1 Binary Weighted DAC . . . . . . . . . . . . . . . . . . . . . 84
6.2.2 Unary Decoded DAC . . . . . . . . . . . . . . . . . . . . . . 86
6.2.3 Segmented DAC . . . . . . . . . . . . . . . . . . . . . . . . 86
6.3 Basic DAC Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.3.1 Intrinsic Accuracy . . . . . . . . . . . . . . . . . . . . . . . 88
6.3.2 Current Source Mismatch . . . . . . . . . . . . . . . . . . . 89
6.4 A V Compensated Current Source . . . . . . . . . . . . . . . . . . 92
th
6.5 Proposed Digital-to-Analog Converter . . . . . . . . . . . . . . . . 94
6.6 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
VII CONCLUSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.1 Main Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . 100
7.2 Research Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
vii
LIST OF TABLES
1 Achievable Bits of Accuracy (FOM) . . . . . . . . . . . . . . . . . . . 19
2 Floating-Gate Retention in 10 Years . . . . . . . . . . . . . . . . . . 31
3 Summary of Floating-Gate Transistor Performance . . . . . . . . . . 33
4 Summary of Amplifier Performance . . . . . . . . . . . . . . . . . . . 44
5 Qualitative Comparison of Different Amplifier Offset Voltage Cancela-
tion Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6 Summary of Voltage Reference Performance . . . . . . . . . . . . . . 61
7 Performance Comparison for Different Voltage References . . . . . . . 62
8 Summary of Current Reference Performance . . . . . . . . . . . . . . 81
9 Performance Comparison for Different CMOS Current References . . 82
viii
LIST OF FIGURES
1 Floating-Gate Transistor: Circuit schematic and layout of a floating-
gate pMOS transistor. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2 Threshold Voltage Modification: Drain current of a floating-gate tran-
sistor as a function of the gate voltage for different ∆Q values in the
floating node. The inset figure emphasizes the sub-threshold region. . 13
3 Electron Tunneling: Cross section of the MOS capacitor along with
the biases required to enable tunneling. . . . . . . . . . . . . . . . . . 14
4 Electron Injection: Cross section of the floating-gate transistor along
with the biases required to enable injection. . . . . . . . . . . . . . . 15
5 Programming Precision: (a) Plot of ∆I as a function of the total ca-
pacitance C on the floating-node for a fixed ∆Q. (b) Plot of the FOM
T
as a function of the initial current for a fixed ∆Q. . . . . . . . . . . . 18
6 Injection Rate Characterization: A plot of ∆I as a function of I for
init
several V values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ds
7 Injection Rate Characterization: A plot of ∆I as a function of V for
ds
a given I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
init
8 Mathematical Modeling of Injection: Variation of model parameters
k , k , and k with V . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1 2 3 ds
9 MathematicalModelingofInjection: (a)Variationofmodelparameter
m with I . (b) Variation of f with I . . . . . . . . . . . . . . 23
initial initial
10 Target Programming: Asymptotic approach toward programming var-
ious target current. . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
11 Programming Accuracy: Average percentage error of a 50 sample data
for a wide range of programmed currents. . . . . . . . . . . . . . . . . 25
12 Analog Storage: (a) Current values for a row of 50 floating-gate tran-
sistors programmed as sine wave of 4nA , 40nA , and 80nA . (b)
pp pp pp
Percentage error for a 40nA sine wave programmed at a DC current
pp
of 1µA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
13 Analog Computational Elements: (a) A 8x8 DCT kernel programmed
onto a floating-gate transistor array around a DC current value of
10nA. (b) Percentage error of the 8x8 DCT kernel. . . . . . . . . . . 27
14 Long Term Retention:(a) Drain current of a floating-gate transistor
in a 0.5µm CMOS process measured over 16 days. (b) Drain current
distribution of a floating-gate transistor current measured over 16 days. 28
ix
15 Charge Retention: Charge loss measured at different temperatures and
time periods as estimated from threshold voltage changes is plotted
using ◦’s along with the extrapolated theoretical fits in solid lines. . 30
16 Amplifier Macromodel: The inherent input referred offset voltage V
os
of the amplifier is canceled by programming an offset current I using
os
floating-gate transistors. . . . . . . . . . . . . . . . . . . . . . . . . . 35
17 Floating-Gate Based Offset Compensation: A circuit implementation
of the proposed offset removal scheme in a single stage folded-cascode
amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
18 Amplifier Die Micrograph: The prototype circuit occupies an area of
115µm×45µm in a 0.5µm CMOS process. . . . . . . . . . . . . . . . 39
19 Offset Programming: Transfer curves of the prototype amplifier config-
ured as a comparator with offset voltages programmed in 10mV steps. 40
20 Offset Cancelation: (a) Plot of the input offset voltage against I −
3
I , programmed in 100µV steps. (b) Optimal voltage cancelation; a
4
minimum offset voltage of 25µV was obtained. . . . . . . . . . . . . . 41
21 Offset Voltage Temperature Sensitivity: Temperature variation of the
input referred offset voltage across for a temperature range of 170oC. 42
22 Offset Voltage Drift: Offset voltage variation as a function of time for
a period of 110 hours. . . . . . . . . . . . . . . . . . . . . . . . . . . 43
23 Conceptual representation of the proposed reference: (a) Schematic
diagram of the proposed approach. (b) Graphical representation of
the proposed approach. . . . . . . . . . . . . . . . . . . . . . . . . . . 47
24 Proposed Voltage Reference #1: Simplified circuit schematic of the
proposed programable voltage reference #1. . . . . . . . . . . . . . . 48
25 Voltage Reference #1 Die Micrograph: Chip micrograph of the proto-
type voltage reference in a 0.35µm CMOS process. . . . . . . . . . . . 51
26 Voltage Reference #1 Programmability: Plot of V against the pro-
ref
grammed voltage difference between M and M . . . . . . . . . . . . 52
2 1
27 VoltageReference#1Accuracy: Datapointanderrorplotforaccurate
programming of V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
ref
28 Voltage Reference #1 Temperature Variation: (a) Voltage reference
variation with temperature for different programmed V values. (b)
ref
Voltage reference variation with temperature for V = 0.4V. . . . . . 54
ref
29 Voltage Reference #1 Temperature Sensitivity: Experimental and the-
oreticalplotsofthereferencevoltagesensitivityagainsttheirrespective
programmed V values. . . . . . . . . . . . . . . . . . . . . . . . . . 55
ref
x