Handbook of 3D Integration Vol. 4: Design, Test, and Thermal Management.

479 Pages·2019·27.435 MB·English

by  Peter Ramm (editor), Muhannad S. Bakir (editor), Paul D. Franzon (editor), Philip Garrou (editor), Mitsumasa Koyanagi (editor), Eric J. Marinissen (editor)

Handbookof3DIntegration
RelatedTitles
Garrou,P.,Bower,C.,Ramm,P.(eds.)
Handbookof3DIntegration
Volumes1and2:TechnologyandApplicationsof3DIntegratedCircuits
2012
PrintISBN:978-3-527-33265-6
Garrou,P.,Koyanagi,M.,Ramm,P.(eds.)
Handbookof3DIntegration
Volume3:3DProcessTechnology
2014
PrintISBN:978-3-527-33466-7
Handbook of 3D Integration
Design,Test,andThermalManagement
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v
Contents
IntroductiontoDesign,TestandThermalManagement
of3DIntegratedCircuits xv
PartI Design 1
1 3DDesignStyles 3
PaulD.Franzon
1.1 Introduction 3
1.2 3D-ICTechnologySet 3
1.3 Why3D 6
1.4 Miniaturization 7
1.5 MemoryBandwidth 8
1.6 3DLogic 10
1.6.1 Power-EfficientComputingandLogic 11
1.6.2 ModularPartitioning:FFTProcessor 12
1.6.3 CircuitPartitioning 13
1.6.4 3DHeterogeneousProcessor 14
1.6.5 ThermalIssues 15
1.7 HeterogeneousIntegration 16
1.8 Conclusions 18
References 18
2 UltrafinePitch3DStackedIntegratedCircuits:Technology,
DesignEnablement,andApplication 21
DragomirMilojevic,PrashantAgrawal,PraveenRaghavan,GeertVanderPlas,
FranckyCatthoor,LiesbetVanderPerre,DimitriosVelenis,RaviVaradarajan,
andEricBeyne
2.1 Introduction 21
2.2 Overviewof3DIntegrationTechnologies 23
2.2.1 IntegrationGranularity 23
2.2.2 StackingOrientation 23
2.2.3 TSVFormation 24
2.3 DesignEnablementofUltrafinePitch3DIntegratedCircuits 25
2.3.1 DesignFlowOverview 25
vi Contents
2.3.2 3DIntegrationBackboneTool 27
2.3.3 3DDesignFlowAdd-Ons 28
2.3.3.1 InterconnectDelayandPowerModels 29
2.3.3.2 RepeaterAreaModel 30
2.3.3.3 CostModel 31
2.4 ImplementationofMobileWirelessApplication 32
2.4.1 ApplicationDriver 32
2.4.2 ArchitectureTemplate 32
2.4.3 MPSoCInstance 34
2.4.4 MultipleMemoryOrganizationandBusStructure 34
2.4.5 ExperimentalSetup 35
2.4.6 ExperimentalResults 36
2.4.6.1 Privatevs.HybridMemoryArchitecture 36
2.4.6.2 InterconnectTechnologyComparison 36
2.4.6.3 ImpactofSystemArchitecture 37
2.4.6.4 SystemParametervs.DesignChoices 38
2.5 Conclusions 38
References 39
3 PowerDeliveryNetworkandIntegrityin3D-ICChips 41
MakotoNagata
3.1 Introduction 41
3.2 PDNStructureandIntegrity 41
3.3 PDNSimulationandCharacterization 43
3.4 PDNin3DIntegration 49
References 52
4 MultiphysicsChallengesandSolutionsfortheDesignof
Heterogeneous3DIntegratedSystem 53
AlexanderSteinhardt,DimitriosPapaioannou,AndyHeinig,
andPeterSchneider
4.1 Introduction 53
4.1.1 Example:Stent 57
4.1.2 ExampleInterposer 59
4.2 DataHandlingfortheSystemView 61
4.3 ElectricalChallenges 62
4.3.1 Modeling 64
4.3.2 Simulation 64
4.3.3 Optimization 65
4.4 MechanicalChallenges 67
4.5 ThermalChallenges 68
4.6 ThermomechanicalChallenges 72
Acknowledgments 77
References 77
Contents vii
®
5 PhysicalDesignFlowfor3D/CoWoS StackedICs 81
Yu-ShiangLin,SandeepK.Goel,JonathanYuan,TomChen,andFrankLee
5.1 Introduction 81
®
5.2 CoWoS vs.3DDesignParadigm 82
5.3 PhysicalDesignChallenges 83
5.4 PhysicalDesignFlow 85
5.4.1 RCExtractionandTSVModeling 85
5.4.2 InterposerConnectivityCheckingTechnique(LVS) 87
5.4.3 InterposerInterfaceAlignmentChecking 88
5.4.4 Cross-DieTimingCheck 90
5.4.5 IRDropAnalysisfortheInterposer 92
5.5 PhysicalDesignGuideline 94
5.5.1 InterposerWideBusRoutingGuideline 94
5.5.2 InterposerSI/PIAnalysisforHBMInterface 97
5.5.3 Combo-BumpDesignStyle 106
5.5.4 Chip-PackageCo-DesignforStackedICs 109
5.5.5 InterposerMulti-DieESDProtectionScheme 110
5.6 TSMCReferenceFlows 113
5.7 Conclusion 114
References 114
6 DesignandCADSolutionsforCoolingandPowerDeliveryfor
Monolithic3D-ICs 115
SandeepSamalandSungK.Lim
6.1 Introduction 115
6.2 NewThermalIssuesinMonolithic3D-ICs 117
6.2.1 MaterialandStructuralDifferences 118
6.2.2 TemperatureMapComparisons 119
6.3 FastThermalAnalysiswithAdaptiveRegression 121
6.3.1 InitialExperiments 121
6.3.2 ModelingTechnique 123
6.3.3 SampleGeneration 123
6.3.4 SimulationResults 124
6.4 NewPowerDeliveryIssuesinMonolithic3D-ICs 126
6.4.1 DesignandAnalysisSetup 126
6.4.2 ImpactofPDN 128
6.4.3 PDNAnalysisResults 131
6.5 PowerDeliveryNetworkOptimization 134
6.5.1 DesignStyles 134
6.5.2 FullPDNAnalysisResults 135
6.5.3 PDNDesignGuidelinesforMonolithic3D-ICs 137
6.6 Conclusions 139
References 139
viii Contents
7 ElectronicDesignAutomationfor3D 141
PaulD.Franzon
7.1 Introduction 141
7.2 EDAFlowsfor3D-IC 141
7.3 CommercialEDASupport 143
7.4 ModularPartitioningApproaches 143
7.5 CircuitPartitioning 145
7.6 Conclusions 146
References 147
8 3DStackedDRAMMemories 149
ChristianWeis,MatthiasJung,andNorbertWehn
8.1 3D-DRAMDesignSpaceandDRAMTechnologyBackground 150
8.1.1 DRAMEvolution 150
8.1.2 CommonDRAMArchitecture 152
8.1.3 ArchitectureStudyofa22nm4GB3D-DRAMCube 155
8.1.4 DRAMMemoryController 158
8.2 DesignSpaceExplorationof3D-DRAMs 160
8.2.1 3D-DRAMBehavioralModels 160
8.2.1.1 PowerModelVerification 162
8.2.2 3D-DRAMCoreArchitectureandTechnology 164
8.2.2.1 WiringandTSVConsiderations 165
8.2.3 3D-DRAMArchitectureExplorationResults 167
8.2.3.1 3D-DRAMBankExplorationResults 167
8.2.3.2 Complete3D-DRAMStackResults 169
8.2.4 FlexibleBurstLengthandBandwidthInterfacefor3D-DRAMs 172
8.2.4.1 ExperimentalResults 173
8.2.4.2 SubsystemPowerandEnergyEstimation 175
8.3 Architectural3DStackedDRAMControllerOptimizations 176
8.3.1 Temperature-AwareRefreshControlfor3DStackedDRAMs 177
8.3.2 Advanced3DStackedDRAMPower-DownPolicies 178
8.3.2.1 StaggeredPowerDownforStandardDDR3DRAMs 179
8.3.2.2 BankwiseStaggeredPowerDownforWideIODRAMs 182
8.4 Conclusion 183
References 184
PartII Test 187
9 CostModelingfor2.5Dand3DStackedICs 189
MottaqiallahTaouil,SaidHamdioui,andErikJanMarinissen
9.1 Introduction 189
9.2 Testing3DStackedICs 189
9.2.1 ImportanceofTesting 189
9.2.2 TestMomentsandTestFlows 190
9.3 CostModeling 191
9.3.1 CostClassification 191
9.3.2 DesignCost 191
Contents ix
9.3.3 ManufacturingCost 191
9.3.4 TestCost 192
9.3.5 PackagingCost 192
9.3.6 LogisticsCost 193
9.4 3D-COSTAR 193
9.4.1 ToolInputsandOutputs 194
9.4.2 ToolFlow 194
9.5 CaseStudies 196
9.5.1 ReferenceCases 196
9.5.2 Experiments 198
9.5.2.1 FaultCoverageofInterposerPre-BondTesting 198
9.5.2.2 Mid-BondTestingandLogistics 199
9.5.2.3 DedicatedProbePadsvs.Micro-BumpProbing 200
9.5.3 FaultCoverageofInterposerPre-BondTesting 202
9.5.4 Mid-BondTestingandLogistics 204
9.5.5 DedicatedProbePadsvs.Micro-BumpProbing 204
9.6 Conclusion 207
References 207
10 InterconnectTestingfor2.5D-and3D-SICs 209
Shi-YuHuang
10.1 Introduction 209
10.2 Pre-BondTSVTesting 211
10.2.1 GeneralTestMethodsforPre-BondTSVs 211
10.2.2 LeakageTestbyVoltageConversionandComparison 213
10.2.3 Charge-and-Sample-BasedPre-BondTSVTest 214
10.2.4 InputSensitivityAnalysis(ISA)-BasedOscillationTest 216
10.2.4.1 ElectricalEffectofaResistiveOpenFault 216
10.2.4.2 ElectricalEffectofaLeakageFault 216
10.2.4.3 TestStructure 217
10.2.4.4 FaultDetectionScheme 218
10.2.4.5 ImpactofProcessVariation 219
10.3 Post-BondInterconnectTesting 220
10.3.1 DirectMeasurement 220
10.3.2 Voltage-Divider-BasedTest 221
10.3.3 Pulse-VanishingTest(PVTest) 222
10.3.4 Characterization-BasedTestMethodviaVOTScheme 225
10.4 ConcludingRemarks 227
References 228
11 Pre-BondTestingThroughDirectProbingofLarge-Array
Fine-PitchMicro-Bumps 231
ErikJanMarinissen,BartDeWachter,JörgKiesewetter,andKenSmith
11.1 Introduction 231
11.2 Pre-BondTesting 232
11.3 Micro-Bumps 234
11.4 ProbeTechnology 236
x Contents
11.4.1 ProbeCards 236
11.4.2 ProbeStation 238
11.5 TestVehicle:Vesuvius-2.5D 239
11.6 ExperimentResults 242
11.6.1 InitialHurdles 242
11.6.2 ProbeMarks 243
11.6.3 PTPAAccuracy 245
11.6.4 ContactResistance 247
11.6.5 ProbeImpactonStackInterconnectYield 248
11.7 Conclusion 249
Acknowledgments 249
References 250
12 3DDesign-for-TestArchitecture 253
ErikJanMarinissen,MarioKonijnenburg,JoukeVerbree,Chun-ChuanChi,
SergejDeutsch,ChristosPapameletis,TobiasBurgherr,KonstantinShibin,
BrionKeller,VivekChickermane,andSandeepK.Goel
12.1 Introduction 253
12.2 Basic3D-DfTArchitecture 254
12.3 Vesuvius-3D3D-DfTDemonstrator 257
12.3.1 Vesuvius-3DTechnology 257
12.3.2 3D-DfTDemonstratorDesign 258
12.3.3 3D-DfTDemonstratorResults 263
12.4 ExtensionstotheBasic3D-DfTArchitecture 265
12.4.1 Multi-towerStacks 265
12.4.2 TestDataCompression 267
12.4.3 HierarchicalSoCsContainingEmbeddedCores 269
12.4.4 At-SpeedInterconnectTesting 270
12.4.5 Memory-on-LogicStacks 272
12.5 Conclusion 276
Acknowledgments 276
References 277
13 OptimizationofTest-AccessArchitecturesandTestScheduling
for3DICs 281
SergejDeutsch,BrandonNoia,KrishnenduChakrabarty,andErikJan
Marinissen
13.1 UncertainParametersinOptimizationof3DTestArchitectureand
TestScheduling 282
13.2 RobustOptimizationof3DTestArchitecture 285
13.2.1 MathematicalModelforRobustCo-optimizationofTestArchitecture
andTestScheduling 286
13.2.2 HeuristicMethodforRobustOptimizationBasedonSimulated
Annealing 290
13.3 SimulationResults 294
13.4 Conclusion 299
References 299