Generation of Accurate OnmChip T1.ansconductances - T-Space

142 Pages·2000·7.42 MB·English

Generation of Accurate OnmChip T1.ansconductances Using a
Monolithic CMOS PLL
With Hybrid Analog and Digital Control
Angus McLaren
A Thesis submitted in conformity with the requirements
for the degree of Master of Applied Science
Department of ElecûicaI and Computer Engineering
University of Toronto
6C opyright Angus McLaren, 2000
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Generation of Accurate OnmChip ansc conductances Using a
MonoIithic CMOS PLL
With Hybrid Analog and Digital Control
Angus McLaren
Department of Electrical and Computer Engineering
University of Toronto
Degne of Master of Applied Science, 200
Abstract
A method for generating accurately-known on-chip transistor transconductances over pro-
cess, power-supply. and temperatun variations is prtsented. The technique uses an adjustable
constant-g, bias circuit, which is tuned with a Nly-integrated CMOS PU. locked to an extemal
frequency reference nomally present to produce a system dock. The PU. uses a charge-pump
structure with three control-bop (two digital and one analog) having overlapping ranges with
hystensis to minimize tuning glitches in steady-state. The PLL has a lock-range of 135 MHz to
300 MHz, and displays an RMS jitter of 15.6 ps. The transconductances generated from the cir-
cuit display a 2.2% variation for a 60°C change in temperature, and a 1.396 variation for a 10%
variation in power-supply voltage. The design has been fabncated in a 0.35 pn CMOS pmcess,
using an active ana of 1200 x 120p m2, and drawing 5.8 mA from a 3.3 V supply.
1w ould like to thank my supervisor. Ken Martin, whose ideas this work was based on. 1a m
deeply indebted to him for the opportunities htg ave m. and the invaluable knowledge he has
passed on to me,
Thanks to the EA104 posse for providiag a lively (sometimes exceedingly) work environment,
indispensable technical and emotional support, ancl, of cow,f riendship. Afshin. Amir, Anas,
Anthony, Augustine, Bahram, Camcron, Dave, Dickson (al1 versions), Fabio the Incredible,
James, John. K a m .P rofessor Phang, Mark (both Irish and not), Raj, Saman, Sebastian, Shahr-
iac, Steve, Takis, Vasilis: may al1 your DRC's run clean!
1 am very grateful to NSERC and the University of Toronto for their financial support, and CO
Micronet for their fabrication services. Thanks also to Professor Salama for allowing me access
to his test equipment,
Thanks slso to Professor Saiarna for giving me permission to use his test equipment, and Jaro
Ristupa for maintaining the CAD tools, as well as tracking down test equipment for me.
1 would aiso like to express my gratitude to my father, who has kept up interest in my work over
the past two yean, despite its lying a great distance outside his field of expertise.
Finally, and most importantly. 1 would like to thank my fiance Maia, without whose support and
undentanding 1c ould not have completed this work.
. . . ........ . . A-
..
L
Tabteof CbnQnts
Table of Contents
.
1 Introduction .................~.............................................................~....
. ............................................
2 Phase-Locked Loops: A Background
2.1 B ~Locop S~UC~UE
....o.o..o.~..o..o.o..o..~.o..o.o..a..o.~..o.~..o..o.o..o.a..a..o.~..o.o..o..~.o..o.o..o..~.o..o.o..o..o.o..o.~..o..o.~..o.o..~..~.a..o.o..o eaoooooooosoooo~~~ooooo~o~~~~~~~~~~~
2.1.1 Block Dia-
....................... ................................... .................
2.1.2 Classes of PLL Systems
2.1.3 Linearized SmallSignal Mode1 ..................................................................
2.1.4 Lwk Metrics .................... ..... .......... ...*.....
t.t
2.L.4.1 Lock-in Range ...........................................................................................................
................................................................................................................
2.1.4.2 Hold Range
2.1.4.3 Pull-in Range ............................ .. ...............................................................................
2.1.4.4 Pull-out Range ...........................................................................................................
202 B k k
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2.2.1 Phase-Frequency Detector With Charge-Pump
2.2.1.1 Phase-Fquency Dettctoc. ........*.*.............................................................................
2.2.1.2C hargt Pump for PFD ...............................................................................................
......................... .. ..............................................*.....*.............
2.2.2 Lwp Filter
.....................................................................
2.2.3 Voltoge-Controlled Oscillator
2.2.3.1 LC Oscillators ..*.....................*............ ........*...........................................................
2.2.3.2 RC Multivibmtors ......................................................................................................
23.3.3 Ring Oscillators .........................................................................................................
...................
2.2.4 Frequency Dividers ..........e.............C*.....+...........................
..........
2.2 J Lwp Equations for Charge-Pump PLL With Lead-Lag Loop Filter ..
M Desi-
h~~~ma.*wwoo,omoooooo.o.*.o.*o..o.m..o.o .ooo.oeo.oo .o.o.*.o.o.o.o..*a..o.o.*.o.a.a.~.*.o.a.o..a.a.o.o.o.a..o..o..a.a.o.e.o.a.o..o.a.o.o.a.o..o.o.o.a.o..o.o.~.o.~.o..*o...a.o..o. ..
23.1 Loop Bandwidth
...
...................
2.3.2 Quality Factor and Natural Frequency ............................
.............................................................................................................
2.3.3 PFD
...*....................*.- ..................................... ................ ...............*.....
23.3.1 k kB~ haviour
2.33.2 Logic Fmily ...... ...........~.....~.............1.......................................................................
.................. ...... .... .............................................................
2.3.4 Charge-Pump
2.3.4.1 Upn>own Symettry ....................................................... ...............................
2.3.4.2 Vafiation of U@wn C~crcnts.. ......................................................w.....n ...... ............ .............
2.3.5 VCO ............................................................................................................
. . - - - - . ..... - "- . a
TiGE of Contents
... .. . . .... .. . .. . . . . . . . . . . . . . . . .. . . . . . . . . ... .. . .
3. Block-Level Modeling and Design
3.1 PLL Shuiaüon h b l e ~ ~ ~ , , , , ~ ~ ~ ~ ~ . ~ ~ , , ~ , , ~ ~ ~ ~ ~ ~ ~ . . ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ . ~ . ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ . ~ ~ ~ ~ ~ ~
3.2 SptmB lock-Levd Description
...............o.o.o.o. m.e.o. .o.o o.o.m..o.w.o*m.,o.o.o.o.o.a.o.*.o.o.o..o. o..o.o. a.o.ao.".o*oo.a.o.o.n*oo.o.o.o.a.o.o*oo.o.o.o.o.o.o.o. .....*...*.
3.2.1 System Description
.................... .................................................................
3.2.2 System Advantages
.................... .......... ....
4. Circuit Design ~........om...................................
.. .. . . . . .. . . . . .. . . . . . . .. . . . .. . .
5. Measurements for Fabricated VCO and P U 93
.
6 Conclusions. ......................................................................*............ 122
Appendix A: VHDL Code for UpIDown Logic ................m..............1.2. 5
......
~ppendixB : Derivation of Delay Through Differential Inverter 128
List of Tables
Chapter 2: Phase-Locked Loops: A Background
...................
Table 2.1: State Assigrment for PFD ...,......C.......~o..~~...~.~~o~...~..~.~.~~.~o..~..~..~
Table 2.2: Formuiae for PFD and Passive Lead-Lag Fi ter.. ...........
Table 2.3: Parameter Values Used for Root Locus Plot .,...... ... ....~..o ~~..o...~.~.o~~..~....~...~o~.o~w.e.~ ....*.*.t......e........- ..
..+.. , *. ..
Chapter 4: Circuit Design for Hybrid Analog/Digital PLL
................... ....
Table 4.1: Opamp Characteristics ...*...........,..
oo.~.......~w.~~.......~.....et.o...~.........~~. ....... ..... .
Table 4.2: Characteristics of Bias Loop ................... **.+*..o.*I..*
..beow**.o....,..**.***...*........
Chapter 5: Meamrements for Fabricated VCO and PLL
.............................. .....
Table 5.1: Surnmary of PLL and Bias System Performance *+o.+.
*.+
List of F m
Chapter 1: Introduction
............,... ....
Figue 1.1. Simpiified Schematic of Constant-Tmsconductance Bias Circuit 2
..........................................................................
Figure 1.2. Schematic for bposed System 3
...................... ....................................................
Figure 1.3. Simplified Schematic for PLL 4
................... .. ..........*....*
Figure 1.4. System Schematic for Low-Cost Wmless Receiver 5
Chapter 2: Phase-Locked Loops: A Background
...................................................................
Figure 2.1: Block Diagram for General PLL
.................... ................................................
Figure 2.2. Simplified Charge-Pump Circuit
.... ...................... ............*.........................
Figure 2.3. Block Diagram for Linearized PLL
..............................................................................................
Figure 2.4. Schematic for PFD
................................................................................
Figure 2.5: Signal-Flow ûraph for PFD
.......
Figure 2.6. PFD Characteristic: a) Ideal(Upper) 6) Non-Zero Delay in Logic (Lower)
...................... ........................ ...........................O........
Figure 2.7. Lead-Lag Loop Filter
Figure 2.8: Schematic for Lead-Lag Loop Filter for Charge-Pump P U( Ibo Redizations)
............................ . ..................
Figure 2.9. Schernatic for Cumnt-Starved Delay Element
............ .... ......**..*..........*.........*
Figure 2.10. Circuit Schematic for Differential hverter
................... .................................
Figure 2.11. Root Locus Plot for Third-Order System ...,
.......................................
Figure 2.12: Behaviour of Root Loci for Varying Values of C1/C2
..................................................................................
Figure 2.13: Step Response for PLL
Figun 2.14. Step Response of PLL at Input to VCO .................................. ..........................
..................................... .........................................
Figure 2.15. Pole-Zero Plot for Filter 1
..............*.......... .. .....***............*.*.............*.
Figure 2.16. Bode Plot for PLL W~thF ilter 1
.*.....*............. . .................*.......................
Figure 2.17. Bode Plot of P Ua t Input to VCO
Chapter 3: System-Level Design for Hybrid AnalogDigital PLL
.........................................................................
Figure 3.1: Simplified Schematic of System
.....................................................................................
Figure 3.2: Frequency Plan for VCO
................... ... ......... .................................*....
Figure 3.3. SIMULINK Schematic foc PFD
..........................
Figun 3.4. Ideal Pm) Signals for VCO in Phase Reference Signal
Figure 3.5. PFD Signais with Delay in NAM) Gate. VCO In Phase Wth Reference ..........
...............................................................
Figure 3.6: Ideal Response of PFD for fvcO > fbf
............... ....................
Figure 3.7. PFD Signais with 0.5 ns NAND Delay. fm > fkf
...................................................
Figure 3.8. Loop Fiter Used for SIMULINK Simulations
................... ....................................
Figure 3.9. Step Responses for Viarious Values oFC2
.............. ... ...... ....................O..............
Figure 3.10. Bode Plots for PLL System Design
..............................................
Figm 3.11. BIo& Diagram of UplDown Control Block
.........................................
Figure 3.12. Block Diagnun of Themblock (Same as Binblock)
..............................................................
Figure 3.13. Signals for UplDown Control BIock
Figure 3.14: Complete SIMULINR System ..........................................................................
...................................................
Figure 3.15: Systern Response to 180 Degrec Phase Error
...................................
Figure 3.16. System Response for03 MHz Frequency Discnpancy
..................... .........
Figure 3.17. System Responsc for Frcquency Dismpancy of 5 MHz
..................... .. ........
Figurc 3.18. Sy stem Response for 75 MHz Frequency Discrepancy
Figure 3.19: Systern Response for 75 M?Iz Frequency Discrepancy and 75 ns bopD elay
Figure 3.20: Response of Altered System to 75 MHz
................. ....... ..... . ..........
Frequency Dimpancy and 75 ns Delay
Chapter 4: Circuit Design for Hybrid Analog/Digital PLL
..... .,.............. *.~......~........~..~....~.~~~.~.~~.~...~~.~.....
Figure 4.1. Simplified System Schematic
....... ...................*........+.*. *.*..................................
Figure 4.2. Full System Block-Diagram
......
Figure 4.3: Circuit Schematic For Adjustable Constant-TransconductanceB ias Circuit
..........................................................
Figure 4.4: Measurement of Bias Circuit Loop Gain
. ............................................ . .
Figure 4.5. Frequency Response of Bias Loop
................................. .........................................
Figure 4.6: Voltage-Controlied Resistor
......................................................
Figure 4.7: Response of Final System to 275 MHz Input
Figure 4.8: Response of Final System to 325 MHz Input ..............................................
................................... ........ ..
Figure 4.9. Variable-Resistor Conductance and g~ Versus Va
.................... .... ......*.............................................................
Figure 4.10. G&O Schematic
Figure 4.1 1: Ring Oscillator Signals at Outputs of Various Stages .......*............... . .......**
..................................................................
Figwe 4.12: Circuit Schematic for VCO Inverter
............... .. .......... ...............................
Figure 4.13. Frequency Response of VCO Invexter
. ................. .....
Figure 4 L4: Simulated Transconductance of mhigh Versus VCO hquency
Figure 4.15: VCO Frequency Versus Binary Control Signal (Analog and Themorneter
.......................................
Contml Signals Fixed at Middle Values)
Figure 4.16. Circuit Schematic for VCO Buffer . ................... . ......~...~...*....*.~*.*~..*.~~*.~~.
.............................
Figure 4.17 : VCO Buffer Signals .......................................................
.......................... ................... ....... .
Figure 4.18. Block Diagram for PFD
.................. ..
Figure 4.19. Mean Value of (UpDown) for Various Values of Gate Delay AR
..............................................................
Figure 4.20. Circuit Schematic for PFD FlipFlop
..........................................................................
Figure 4.21. PFD Response for fvco > fkf
Figure 4.22. Response of PFD for Maximum Phase Error at 333.3 MHz ........ ............. .
.....
Figun 4.23. Mean Value of Up-Down ViusP hase EIror Between Inputs at 333 MIIz
...
......... .............. . . . . .
Figure 4.2424:I nitial Circuit Schematic for Charge-Pump
*
..................................
Figure 4.25: Circuit Schematic for Revised Charge-Ump Design
Figure 4.26: ChargclDischarge Cumnts and Output Voltage of Charge-Pump