Generating High Accuracy Timing Signals For Time Driven Switching From GPS Receivers Using ...

91 Pages·2007·22.35 MB·English

by  Leonardo Gasparini

Faculty of Engineering
Master Thesis on
Telecommunication Engineering
Generating
High Accuracy Timing Signals
For Time Driven Switching
From GPS Receivers
Using an FPGA Discrete Filter
Advisor Author
Dr. Andrea Boni Leonardo Gasparini
Co-advisor
Dr. Giorgio Fontana
Academic Year 2005/2006

To my sweet grandma, Corinna
Alla mia dolce nonna, Corinna

Acknowledgements
Per lunghi giorni e lunghe notti, sono molte le persone che mi hanno sopportato in
questi mesi di fatiche, ed `e con piacere che a questo punto il mio pensiero si rivolge
a loro.
Il mio primo ringraziamento, il piu` importante, lo dedico alla mia bella Teresa,
per avermi pensato ogni giorno, ogni ora, ogni minuto e, chiss`a, ogni secondo della
giornata in un periodo di ansie e schizofrenie, per aver accettato di vivere con me
momenti difficili che presto scompariranno.
Un grazie a tutta la mia famiglia: il re Sandro e la regina Ester, il fratellone
BrunoelanonnaCorinna,chemihannoincoraggiatointuttiimodimasoprattutto
per avermi permesso di uscire dal tunnel dei panini e delle pizzette con piatti
prelibati settimanalmente recapitati in via Borino.
Un abbraccio anche alla zia Grazia, agli zii Paola e Giancarlo, Costante e Paola,
Federico ed Anna, a tutti i cugini ed in particolare a Iaio, guru della mia vita.
Grazie al mio cane Paco, per aver morsicato il cavo del trasformatore del mio
portatile senza restarci secco.
Come vuole la tradizione, un particolare pensiero lo dedico alla mia seconda
famiglia, la famiglia Peterson: Camicia di Forza per essere stato in grado di trovare
qualsiasi cosa io perdessi, Gonzo per aver digerito a suon di risate tutti gli insulti
che gli ho rivolto, Matrix e Rimba per aver subito i miei scherzi quasi senza batter
ciglio (al massimo un po’ di tachicardia), la zia Sam e lo zio Umbe per le ottime
cene a base di zampone ed infine il gemello Collasso, emigrato lontano, ma che ogni
tanto ritorna a farsi un pisolino. Grazie anche ad Aldo e alla Antonia, per avermi
concesso di vivere in una casa cos`ı calda e spaziosa.
Un grazie a tutti i miei amici: 100, Burgy, Cerro, Enrico, Fulmine, Mattia e
Lisa, Napo, Nicola, PieroBZ, Pilota, Tonino, Virile, i compagni del Buena e delle
v
mitiche feste ai campi e tutti quelli dimenticati. Un abbraccio anche a Pierluca,
che cotidianamente ritorna nei miei pensieri.
Lamiaesperienzainfacolt`anonsarebbestatalastessasenzal’allegriadiBurgy,
Giambo, Mattia Broilo, la Vale, e l’incomprensibilit`a delle parole degli Erasmus
dalle valli trentine, ovvero Chini, Dal Follo, Endrici, Gionta e Zadra.
Thanks also to ChessMaster Troy Goldschmidt, who never let me turn to the
Dark Side of the Force, and all the people I’ve been living with during my Erasmus
experience in Helsinki.
I would like to thank also Dr. Andrea Boni, Dr. Giorgio Fontana and Dr. Ofek
for having given me the chance to partecipe to this project, Francesco, Franco,
Luca and Michele for their help during the hard days of work in the laboratory of
electronics.
In the end, thanks to David Pajo and the Dirty Three, whose celestial music
defeated my sleeplessness.
Contents
Acknowledgements v
List of Figures ix
List of Tables xi
Introduction xv
1 Background and objectives 1
1.1 the IP-FLOW project . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 Principles of operation . . . . . . . . . . . . . . . . . . . . . 2
1.1.2 Timing signals . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1.3 The prototype . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2.1 Accuracy requirements . . . . . . . . . . . . . . . . . . . . . 10
1.2.2 Previous configuration . . . . . . . . . . . . . . . . . . . . . 12
2 Devices and instruments 17
2.1 Main devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1.1 GPS receiver #1 . . . . . . . . . . . . . . . . . . . . . . . . 19
2.1.2 FPGA #1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2 Other devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.1 FPGA #2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2.2 Function generator . . . . . . . . . . . . . . . . . . . . . . . 22
2.2.3 Oscilloscope . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2.4 Universal counter . . . . . . . . . . . . . . . . . . . . . . . . 23
vii
viii CONTENTS
2.2.5 GPS receiver #2 . . . . . . . . . . . . . . . . . . . . . . . . 24
2.3 The FPGA-related software . . . . . . . . . . . . . . . . . . . . . . 24
2.4 Data acquisition related software . . . . . . . . . . . . . . . . . . . 29
3 The principle of working 35
3.1 Practical problems . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.2 Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4 The implementation phase 41
4.1 The VHDL components . . . . . . . . . . . . . . . . . . . . . . . . 42
4.1.1 Reset generation . . . . . . . . . . . . . . . . . . . . . . . . 42
4.1.2 1PPS signal period measurement and division calculation . . 43
4.1.3 1PPS signal period correctness check . . . . . . . . . . . . . 45
4.1.4 Output generation . . . . . . . . . . . . . . . . . . . . . . . 47
4.2 Test phase and corrections . . . . . . . . . . . . . . . . . . . . . . . 48
4.2.1 The asynchronous input issue . . . . . . . . . . . . . . . . . 48
4.2.2 The input rise time issue . . . . . . . . . . . . . . . . . . . . 48
4.2.3 Jitter and drift . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.3 Input signal filtering . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.4 FIR filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.4.1 FIR filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
4.4.2 PID controller . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5 Final results 63
6 Conclusions 67
6.1 Final remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.2 Further developments . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Bibliography 71
List of Figures
1.1 Common Time Reference structure. . . . . . . . . . . . . . . . . . . 4
1.2 Example of packet flowing in a UTC-based pipeline forwarding ar-
chitecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 Fractional λ switch architecture and operating stages. . . . . . . . . 6
1.4 Functional diagram of a Time Driven Switch. . . . . . . . . . . . . 7
1.5 Testbed functional diagram. . . . . . . . . . . . . . . . . . . . . . . 9
1.6 Phase-Locked Loop - Scheme of principle. . . . . . . . . . . . . . . 13
1.7 Block Scheme of the Tekelec’s Epsilon Board II. . . . . . . . . . . 13
1.8 Hardware setup of the Tekelec’s Epsilon Board OEM II. . . . . . 14
1.9 Tekelec’s Epsilon Board OEM II. . . . . . . . . . . . . . . . . . 14
2.1 Final system. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2 U-BLOX’s LEA-4T GPS receiver. . . . . . . . . . . . . . . . . . . 18
2.3 ComBlock’s COM-1300. . . . . . . . . . . . . . . . . . . . . . . . 20
2.4 UBlox’s LEA-4T circuit board. . . . . . . . . . . . . . . . . . . . . 21
2.5 Digilent’s Spartan-3 Starter Board. . . . . . . . . . . . . . . . . 23
2.6 Rise time comparison between the three receivers. . . . . . . . . . . 25
2.7 Xilinx ISE 8.1 graphical interface. . . . . . . . . . . . . . . . . . . 26
2.8 Xilinx ModelSim output example. . . . . . . . . . . . . . . . . . . 27
2.9 Xilinx PACE graphical interface. . . . . . . . . . . . . . . . . . . . 29
2.10 Xilinx iMPACT - Programming type selection. . . . . . . . . . . . 30
2.11 Xilinx iMPACT - JTAG programming window. . . . . . . . . . . . 30
2.12 Oscilloscope’s data acquisition.vi - Front panel: inputs. . . . . . . . 31
2.13 Oscilloscope’s data acquisition.vi - Front panel: output 1. . . . . . . 32
2.14 Oscilloscope’s data acquisition.vi - Front panel: output 2. . . . . . . 33
ix
x LIST OF FIGURES
3.1 Basic algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.2 Temporal window. . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.3 Reminder distortion. . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.4 Reminder recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.1 Moore vs. Mealy machine. . . . . . . . . . . . . . . . . . . . . . . . 49
4.2 Pure 1PPS vs. Sampled 1PPS (enlarged detail on the right). . . . . 50
4.3 Tekelec’sEpsilonBoardIIvsU-Blox’sLEA-4T:delaytimeprogress,
histogram and time sliced histogram using a sliding window. . . . . 52
4.4 Tekelec’sEpsilon Board IIvsTrimble’sResolution T:delaytime
progress, histogram and time sliced histogram using a sliding window. 53
4.5 U-Blox’sLEA-4TvsTrimble’sResolution T:delaytimeprogress,
histogram and time sliced histogram using an enlarging window. . . 54
4.6 FIR filter in the direct structure. . . . . . . . . . . . . . . . . . . . 56
4.7 FIR filter in the transposed structure. . . . . . . . . . . . . . . . . . 56
4.8 The implemented FIR filter. . . . . . . . . . . . . . . . . . . . . . . 58
4.9 The implemented PID controller. . . . . . . . . . . . . . . . . . . . 60
4.10 Step responses of the PID controller. . . . . . . . . . . . . . . . . . 62
5.1 1000 seconds long acquisitions of 1PPS signals delay. . . . . . . . . 66