Future Tendencies in Computer Science, Control and Applied Mathematics: International Conference on the Occasion of the 25th Anniversary of INRIA Paris, France, December 8–11, 1992 Proceedings

1050 Pages·1992·4.68 MB·English

by  J. L. Lions (auth.), A. Bensoussan, J. -P. Verjus (eds.)

Preface
Computerscienceandengineeringcurriculahavebeenevolvingatafasterpacetokeepupwith
thedevelopmentsinthearea. Thisoftendictatesthattraditionalcourseswillhavetobecom-
pressedtoaccommodatenewcourses. In particular, itisnolonger possiblein thesecurricula
to include separate courses on digital logic, assembly language programming, and computer
organization.Often,thesethreetopicsarecombinedintoasinglecourse.Thecurrenttextbooks
inthemarketcatertotheold-stylecurriculainthesedisciplines,withseparatebooksavailable
oneachofthesesubjects. Mostcomputerorganizationbooksdonotcoverassemblylanguage
programminginsufficientdetail. Thereisadefiniteneedtosupportthecoursesthatcombine
assembly language programming and computer organization. This is the main motivation for
writing this book. It provides a comprehensive coverage of digital logic, assembly language
programming,andcomputerorganization.
Intended Use
Thisbookisintendedasanundergraduatetextbookforcomputerorganizationcoursesoffered
by computer science and computer engineering/electrical engineering departments. Unlike
othertextbooksinthisarea,thisbookprovidesextensivecoverageofassemblylanguagepro-
gramminganddigitallogic. Thus,thebookservestheneedsofcompressedcourses.
In addition, it can be used as a text in vocational training courses offered by community
colleges. Because of the teach-by-example style used in the book, it is also suitable for self-
studybycomputerprofessionalsandengineers.
vii
viii Preface
Prerequisites
Theobjectiveistosupportavarietyofcoursesoncomputerorganizationincomputerscience
and engineering departments. To satisfy this objective, we assume very little background on
thepartofthestudent. Thestudentisassumedtohavehadsomeprogrammingexperienceina
structured,high-levellanguagesuchasCorJava™.Thisisthebackgroundalmostallstudents
in computer science and computer engineering programs typically acquire in their first year
of study. This prerequisite also implies that the student has beenexposedto the basicsof the
software-developmentcycle.
Features
Hereisasummaryofthespecialfeaturesthatsetthisbookapart:
• Mostcomputerorganizationbooksassumethatthestudentshavedoneaseparatedigital
logic course before taking the computer organization course. As a result, digital logic
is covered in an appendix to provide an overview. This book provides detailed cover-
age of digital logic, including sequential logic circuit design. Three complete chapters
aredevotedtodigitallogictopics,wherestudentsareexposedtothepracticalsidewith
detailsonseveralexampledigitallogicchips. Thereisalsoinformationondigitallogic
simulators. Studentscanconvenientlyusethesesimulatorstotesttheirdesigns.
• Thisbookprovidesextensivecoverageofassemblylanguageprogramming,comprising
assemblylanguageofbothCISCandRISCprocessors. WeusethePentiumastherep-
resentative of the CISC category and devote more than five chapters to introducing the
Pentium assembly language. The MIPS processor is used for RISC assembly language
programming. Inbothcases,studentsactuallywriteandtestworkingassemblylanguage
programs. The book’s homepage has instructions on downloading assemblers for both
PentiumandMIPSprocessors.
• Weintroduceconceptsfirstinsimpletermstomotivatethereader. Later,werelatethese
conceptsto practical implementations. In the digital logic part, weuse severalchips to
showthetypeofimplementationsdoneinpractice. Fortheothertopics,weconsistently
use three processors—the Pentium, PowerPC, and MIPS—to cover the CISC to RISC
range. Inaddition,weprovidedetailsontheItaniumandSPARCprocessors.
• Most textbooks in the area treat I/O and interrupts as an appendage. As a result, this
topicisdiscussedverybriefly. Consequently,studentsdonotgetanypracticalexperience
on how interrupts work. In contrast, we use the Pentium to illustrate their operation.
Severalassemblylanguageprogramsareusedtoexplaintheinterruptconcepts. Wealso
show how interrupt service routines can be written. For instance, one example in the
chapteroninterruptsreplacesthesystem-suppliedkeyboardserviceroutinebyourown.
By understanding the practical aspects of interrupt processing, students can write their
ownprogramstoexperimentwithinterrupts.
Preface ix
• Ourcoverageofsystembusesiscomprehensiveandup-to-date. Wedivideourcoverage
into internal and externalbuses. Internal busesdiscussedinclude the ISA, PCI, PCI-X,
AGP,andPCMCIAbuses.OurexternalbuscoverageincludestheEIA-232,SCSI,USB,
andIEEE1394(FireWire)serialbuses.
• Extensive assembly programming examples are used to illustrate the points. A set of
inputandoutputroutinesisprovidedsothatthereadercanfocusondevelopingassembly
languageprogramsratherthanspendingtimeinunderstandinghowinputandoutputcan
bedoneusingthebasicI/Ofunctionsprovidedbytheoperatingsystem.
• We do not use fragments of assembly language code in examples. All examples are
complete in the sense that they can be assembled and run to give a better feeling as to
howtheseprogramswork.
• AllexamplesusedinthetextbookandotherproprietaryI/Osoftwareareavailablefrom
thebook’shomepage(www.scs.carleton.ca/˜sivarama/org_book). Inad-
dition,thisWebsitealsohasinstructionsondownloadingthePentiumandMIPSassem-
blerstogiveopportunitiesforstudentstoperformhands-onassemblyprogramming.
• Mostchaptersarewritteninsuchawaythateachchaptercanbecoveredintwoorthree
60-minutelecturesbygivingproperreadingassignments. Typically,importantconcepts
areemphasizedinthelectureswhileleavingtheothermaterialinthebookasareading
assignment.Ouremphasisonextensiveexamplesfacilitatesthispedagogicalapproach.
• Interchapterdependenciesarekepttoaminimumtooffermaximumflexibilitytoinstruc-
torsinorganizingthematerial.Eachchapterclearlyindicatestheobjectivesandprovides
anoverviewatthebeginningandasummaryandkeytermsattheend.
Instructional Support
Thebook’sWebsitehascompletechapter-by-chapterslidesforinstructors. Instructorscanuse
theseslidesdirectlyintheirclassesorcanmodifythemtosuittheirneeds. Pleasecontactthe
authorifyouwantthePowerPointsourceoftheslides. Copiesoftheseslides(fourperpage)
are alsoavailablefor distribution to students. In addition, instructors canobtain the solutions
manual by contacting the publisher. For more up-to-date details, please see the book’s Web
pageatwww.scs.carleton.ca/˜sivarama/org_book.
Overview and Organization
Thebookisdividedintoeightparts.Inaddition,Appendicesprovideusefulreferencematerial.
Part I consists of a single chapter and gives an overview of basic computer organization and
design.
Part II presents digital logic design in three chapters—Chapters 2, 3, and 4. Chapter 2
covers the digital logic basics. We introduce the basic concepts and building blocks that we
use in the later chapters to build more complex digital circuits such as adders and arithmetic
logic units (ALUs). This chapter also discusses the principles of digital logic design using
Boolean algebra, Karnaugh maps, and Quine–McCluskey methods. The next chapter deals
x Preface
with combinational circuits. We present the design of adders, comparators, and ALUs. We
also show how programmable logic devices can be used to implement combinational logic
circuits. Chapter4coverssequentiallogiccircuits. Weintroducetheconceptoftimethrough
clock signals. We discuss both latches and flip-flops, including master–slave JK flip-flops.
Theseelementsformthebasisfordesigningmemoriesinalaterchapter.Afterpresentingsome
example sequential circuits such as shift registers and counters, we discuss sequential circuit
design in detail. These three chapters together cover the digital logic topic comprehensively.
Theamountoftimespentonthispartdependsonthebackgroundofthestudents.
Part III deals with system interconnection structures. We divide the system buses into in-
ternalandexternalbuses. Ourclassificationisbasedonwhetherthebusinterconnectscompo-
nentsthataretypicallyinsideasystem.PartIIIconsistsofChapter5andcoversinternalsystem
buses.Westartthischapterwithadiscussionofsystembusdesignissues.Wediscussbothsyn-
chronousandasynchronousbuses. Wealsointroduceblocktransferbuscyclesaswellaswait
states.Busarbitrationschemesaredescribednext.Wepresentfiveexamplebusesincludingthe
ISA,PCI,PCI-X,AGP,andPCMCIAbuses.TheexternalbusesarecoveredinPartVIII,which
discussestheI/Oissues.
PartIVconsistsofthreechaptersanddiscussesprocessordesignissues.Chapter6presents
thebasicsofprocessororganizationandperformance. Wediscussinstructionsetarchitectures
andinstructionsetdesignissues. Thischapteralsocoversmicroprogrammedcontrol. Inaddi-
tion, processorperformance issues, including the SPEC benchmarks, are discussed. The next
chapter gives details about the Pentium processor. The information presented in this chapter
isusefulwhenwediscussPentiumassemblylanguageprogramminginPartV.Pipeliningand
vectorprocessorsarediscussedinthelastchapterofthispart. WeusetheCrayX-MPsystem
to look at the practical side of vector processors. After covering the material in Chapter 6,
instructorscanchoosethematerialfromChapters7and8tosuittheircourserequirements.
Part VcoversPentium assemblylanguageprogramming indetail. There are fivechapters
inthispart. Chapter9providesanoverviewofthePentiumassemblylanguage. Allnecessary
basicfeaturesarecoveredinthischapter. Afterreadingthischapter,studentscanwritesimple
Pentiumassemblyprogramswithoutneedingtheinformationpresentedinthelaterfourchap-
ters. Chapter10describesthePentiumaddressingmodesindetail. Thischaptergivesenough
information for the student to understand why CISC processors provide complex addressing
modes. Thenextchapterdealswithprocedures. Ourintentistoexposethestudenttotheun-
derlyingmechanicsinvolvedinprocedurecalls,parameterpassing,andlocalvariablestorage.
Inaddition,recursiveproceduresareusedtoexploretheprinciplesinvolvedinhandlingrecur-
sion. In all these activities, the important role played by the stack is illustrated. Chapter 12
describesthePentiuminstructionset. OurgoalisnottopresentthecompletePentiuminstruc-
tions, but a representative sample. Chapter 13 deals with the high-level language interface,
whichallowsmixed-modeprogramming inmore thanonelanguage. WeuseCandassembly
languagetoillustratetheprinciplesinvolvedinmixed-modeprogramming. Eachchapteruses
severalexamplestoshowhowvariousPentiuminstructionsareused.
Part VI covers RISC processors in two chapters. The first chapter introduces the general
RISCdesignprinciples. ItalsopresentsdetailsabouttwoRISCprocessors: thePowerPCand
Preface xi
IntelItanium. AlthoughbothareconsideredRISCprocessors,theyalsohavesomeCISCfea-
tures. We discuss a pure RISC processor in the next chapter. The Itanium is Intel’s 64-bit
processor that not only incorporates RISC characteristics but also several advanced architec-
turalfeatures. Thesefeaturesincludeinstruction-levelparallelism,predication,andspeculative
loads. The second chapter in this part describes the MIPS R2000 processor. The MIPS sim-
ulator SPIM runs the programs written for the R2000 processor. We present MIPS assembly
languageprogramsthatarecompleteandrunontheSPIM.Theprogramswepresenthereare
the same programs we have written in the Pentium assembly language (in Part V). Thus, the
readerhasanopportunitytocontrastthetwoassemblylanguages.
PartVIIconsistsofChapters16through18andcoversmemorydesignissues. Chapter16
buildsonthedigitallogicmaterialpresentedinPartII.Itdescribeshowmemoryunitscanbe
constructed using the basic latches and flip-flops presented in Chapter 4. Memory mapping
schemes,bothfull-andpartial-mapping,arealsodiscussed. Inaddition,wediscusshowinter-
leaved memories are designed. The next chapter covers cache memory principles and design
issues. Weuseanextensivesetofexamplestoillustratethecacheprinciples. Towardtheend
ofthechapter,welookatexamplecacheimplementationsinthePentium,PowerPC,andMIPS
processors. Chapter 18 discusses virtual memory systems. Note that our coverage of virtual
memory is from the computer organization viewpoint. As a result, we do not coverthose as-
pectsthatareofinterestfromtheoperating-systempointofview.Aswiththecachememory,we
lookatthevirtualmemoryimplementationsofthePentium,PowerPC,andMIPSprocessors.
ThelastpartcoverstheI/Oissues. WecoverthebasicI/Ointerface issuesin Chapter19.
We start with I/O address mapping and then discuss three techniques often used to interface
withI/Odevices:programmedI/O,interrupt-drivenI/O,andDMA.Wediscussinterrupt-driven
I/O in detail in the next chapter. In addition, this chapter also presents details about external
buses.Inparticular,wecovertheEIA-232,USB,andIEEE1394serialinterfacesandtheSCSI
parallel interface. The last chapter covers Pentium interrupts in detail. We use programming
examples to illustrate interrupt-driven access to I/O devices. We also present an example to
showhowuser-definedinterruptserviceroutinescanbewritten.
Theappendicesprovideawealthofreferencematerialneededbythestudent. AppendixA
primarilydiscussescomputerarithmetic. CharacterrepresentationisdiscussedinAppendixB.
AppendixCgivesinformationontheuseofI/OroutinesprovidedwiththisbookandthePen-
tium assembler software. The debugging aspect of assembly language programming is dis-
cussedin Appendix D. Appendix E givesdetails on running the Pentium assemblyprograms
onaLinuxsystemusingtheNASMassembler. AppendixFgivesdetailsondigitallogicsim-
ulators. Details on the MIPS simulator SPIM are in Appendix G. Appendix H describes the
SPARCprocessorarchitecture. Finally,selectedPentiuminstructionsaregiveninAppendixI.
Acknowledgments
Severalpeoplehavecontributedtothewritingofthisbook. Firstandforemost,Iwouldliketo
thankmywife,Sobha,andmydaughter,Veda,forenduringmypreoccupationwiththisproject.
I thank WayneYuhasz, ExecutiveEditor atSpringer-Verlag, for hisinput and feedbackin
xii Preface
developingthisproject. Hisguidanceandcontinuedsupportfortheprojectaregreatlyappreci-
ated. IalsowanttothankWayneWheeler,AssistantEditor,forkeepingtrackoftheprogress.
He has always been prompt in responding to my queries. Thanks are also due to the staff at
Springer-VerlagNewYork,Inc.,particularlyFrancineMcNeill,foritseffortsinproducingthis
book. I would also like to thank Valerie Greco for doing an excellent job of copyediting the
text.
MysincereappreciationgoestotheSchoolofComputerScienceatCarletonUniversityfor
allowingmetousepartofmysabbaticalleavetocompletethisbook.
Feedback
Works of this nature are never error-free, despite the best efforts of the authors and others
involvedintheproject. Iwelcomeyourcomments,suggestions,andcorrectionsbyelectronic
mail.
Ottawa,Ontario,Canada SivaramaP.Dandamudi
December2001 [email protected]
http://www.scs.carleton.ca/˜sivarama
Contents
Preface vii
PARTI:Overview 1
1 OverviewofComputerOrganization 3
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1.1 BasicTermsandNotation . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Programmer’sView . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2.1 AdvantagesofHigh-LevelLanguages . . . . . . . . . . . . . . . . . . . . . 10
1.2.2 WhyPrograminAssemblyLanguage?. . . . . . . . . . . . . . . . . . . . . 11
1.3 Architect’sView. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.4 Implementer’sView . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.5 TheProcessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.5.1 Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5.2 RISCandCISCDesigns . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.6 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.6.1 BasicMemoryOperations . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.6.2 ByteOrdering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.6.3 TwoImportantMemoryDesignIssues . . . . . . . . . . . . . . . . . . . . . 24
1.7 Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.8 Interconnection: TheGlue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.9 HistoricalPerspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.9.1 TheEarlyGenerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.9.2 VacuumTubeGeneration: Aroundthe1940sand1950s . . . . . . . . . . . 31
1.9.3 TransistorGeneration: Aroundthe1950sand1960s . . . . . . . . . . . . . 32
1.9.4 ICGeneration: Aroundthe1960sand1970s . . . . . . . . . . . . . . . . . 32
1.9.5 VLSIGenerations: SincetheMid-1970s . . . . . . . . . . . . . . . . . . . . 32
1.10 TechnologicalAdvances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.11 SummaryandOutline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
1.12 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
xiii
xiv Contents
PARTII:DigitalLogicDesign 39
2 DigitalLogicBasics 41
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.2 BasicConceptsandBuildingBlocks . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.2.1 SimpleGates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.2.2 CompletenessandUniversality . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.2.3 ImplementationDetails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.3 LogicFunctions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.3.1 ExpressingLogicFunctions . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.3.2 LogicalCircuitEquivalence . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.4 BooleanAlgebra . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.4.1 BooleanIdentities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
2.4.2 UsingBooleanAlgebraforLogicalEquivalence . . . . . . . . . . . . . . . 54
2.5 LogicCircuitDesignProcess . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2.6 DerivingLogicalExpressionsfromTruthTables . . . . . . . . . . . . . . . . . . . . 56
2.6.1 Sum-of-ProductsForm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.6.2 Product-of-SumsForm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
2.6.3 BruteForceMethodofImplementation . . . . . . . . . . . . . . . . . . . . 58
2.7 SimplifyingLogicalExpressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.7.1 AlgebraicManipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.7.2 KarnaughMapMethod . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.7.3 Quine–McCluskeyMethod . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.8 GeneralizedGates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.9 MultipleOutputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
2.10 ImplementationUsingOtherGates . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
2.10.1 ImplementationUsingNANDandNORGates . . . . . . . . . . . . . . . . 75
2.10.2 ImplementationUsingXORGates . . . . . . . . . . . . . . . . . . . . . . . 77
2.11 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
2.12 WebResources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
2.13 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3 CombinationalCircuits 83
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.2 MultiplexersandDemultiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
3.2.1 Implementation: AMultiplexerChip. . . . . . . . . . . . . . . . . . . . . . 86
3.2.2 EfficientMultiplexerDesigns . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.2.3 Implementation: A4-to-1MultiplexerChip . . . . . . . . . . . . . . . . . . 87
3.2.4 Demultiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.3 DecodersandEncoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.3.1 DecoderChips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
3.3.2 Encoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Contents xv
3.4 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.4.1 AComparatorChip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.5 Adders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
3.5.1 AnExampleAdderChip . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
3.6 ProgrammableLogicDevices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
3.6.1 ProgrammableLogicArrays(PLAs) . . . . . . . . . . . . . . . . . . . . . . 98
3.6.2 ProgrammableArrayLogicDevices(PALs) . . . . . . . . . . . . . . . . . . 100
3.7 ArithmeticandLogicUnits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
3.7.1 AnExampleALUChip. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
3.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
3.9 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4 SequentialLogicCircuits 109
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.2 ClockSignal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
4.3 Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
4.3.1 SRLatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
4.3.2 ClockedSRLatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
4.3.3 DLatch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
4.4 Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
4.4.1 DFlip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
4.4.2 JKFlip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.4.3 ExampleChips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
4.5 ExampleSequentialCircuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.5.1 ShiftRegisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.5.2 Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
4.6 SequentialCircuitDesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4.6.1 BinaryCounterDesignwithJKFlip-Flops . . . . . . . . . . . . . . . . . . 127
4.6.2 GeneralDesignProcess . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
4.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
4.8 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
PARTIII:Interconnection 145
5 SystemBuses 147
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
5.2 BusDesignIssues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
5.2.1 BusWidth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
5.2.2 BusType . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
5.2.3 BusOperations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
5.3 SynchronousBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
5.3.1 BasicOperation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
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5.3.2 WaitStates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
5.3.3 BlockTransfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
5.4 AsynchronousBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
5.5 BusArbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
5.5.1 DynamicBusArbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
5.5.2 ImplementationofDynamicArbitration . . . . . . . . . . . . . . . . . . . . 161
5.6 ExampleBuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
5.6.1 TheISABus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
5.6.2 ThePCIBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
5.6.3 AcceleratedGraphicsPort(AGP) . . . . . . . . . . . . . . . . . . . . . . . 180
5.6.4 ThePCI-XBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
5.6.5 ThePCMCIABus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
5.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
5.8 WebResources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
5.9 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
PARTIV:Processors 195
6 ProcessorOrganizationandPerformance 197
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
6.2 NumberofAddresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
6.2.1 Three-AddressMachines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
6.2.2 Two-AddressMachines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
6.2.3 One-AddressMachines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
6.2.4 Zero-AddressMachines . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
6.2.5 AComparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
6.2.6 TheLoad/StoreArchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . 206
6.2.7 ProcessorRegisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
6.3 FlowofControl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
6.3.1 Branching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
6.3.2 ProcedureCalls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
6.4 InstructionSetDesignIssues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
6.4.1 OperandTypes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
6.4.2 AddressingModes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
6.4.3 InstructionTypes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
6.4.4 InstructionFormats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
6.5 MicroprogrammedControl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
6.5.1 HardwareImplementation . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
6.5.2 SoftwareImplementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
6.6 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
6.6.1 PerformanceMetrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237
6.6.2 ExecutionTimeCalculation . . . . . . . . . . . . . . . . . . . . . . . . . . 238