Download Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications PDF Free - Full Version
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About Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications
The most important issue confronting CMOS technology is the power explosion of chips arising from the scaling law. Fully-depleted (FD) SOI technology provides a promising low-power solution to chip implementation. Ultralow-power VLSIs, which have a power consumption of less than 10 mW, will be key components of terminals in the coming ubiquitous-IT society. Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications addresses the problem of reducing the supply voltage of conventional circuits for ultralow-power operation and explains power-efficient MTCMOS circuit design for FD-SOI devices at a supply voltage of 0.5 V.
Detailed Information
| Author: | Takayasu Sakurai, Akira Matsuzawa, Takakuni Douseki |
|---|---|
| Publication Year: | 2010 |
| ISBN: | 1441939776 |
| Pages: | 420 |
| Language: | English |
| File Size: | 10.354 |
| Format: | |
| Price: | FREE |
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