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108 Pages·2005·0.76 MB·English

LinköpingStudiesinScienceandTechnology
DissertationNo. 992
Efficient High-Speed On-Chip
Global Interconnects
Peter Caputa
ElectronicDevices
DepartmentofElectricalEngineering
LinköpingUniversity,SE-58183Linköping,Sweden
Linköping2006
ISBN91-85457-87-6
ISSN0345-7524
ii
EfficientHigh-SpeedOn-Chip
GlobalInterconnects
PeterCaputa
ISBN91-85457-87-6
Copyright(cid:13)c PeterCaputa,2006
LinköpingStudiesinScienceandTechnology
DissertationNo. 992
ISSN0345-7524
ElectronicDevices
DepartmentofElectricalEngineering
LinköpingUniversity
SE-58183Linköping
Sweden
CoverImage
Microphotographofatestchipfabricatedin0.18(cid:22)mCMOS.Thechip
carriesavelocity-of-light-limited5.4mmlongglobalbusandareceiver
basedontheSynchronousLatencyInsensitiveDesignscheme.
PrintedbyLiU-Tryck,LinköpingUniversity
Linköping,Sweden,2006
Abstract
Thecontinuousminiaturizationofintegratedcircuitshasopenedthepathtowards
System-on-Chip realizations. Process shrinking into the nanometer regime im-
provestransistorperformancewhilethedelayofglobalinterconnects,connecting
circuitblocksseparatedbyalongdistance,significantlyincreases. Infact,global
interconnectsextendingacrossafullchipcanhaveadelaycorrespondingtomul-
tiple clock cycles. At the same time, global clock skew constraints, not only
between blocks but also along the pipelined interconnects, become even tighter.
On-chip interconnects have always been considered RC-like, that is exhibiting
longRC-delays. Thishas motivatedlargeeffortsonalternativessuchas on-chip
opticalinterconnects,whichhavenotyetbeendemonstrated,orcomplexschemes
utilizingon-chipRF-transmissionorpulsedcurrent-modesignaling.
In this thesis,we showthatwell-designedelectrical global interconnects, be-
havingastransmissionlines,havethecapacityofveryhighdatarates(higherthan
canbedeliveredbytheactualprocess)andsupportnearvelocity-of-lightdelayfor
single-ended voltage-mode signaling, thus mitigating the RC-problem. We crit-
ically explore key interconnect performance measures such as data delay, max-
imum data rate, crosstalk, edge rates and power dissipation. To experimentally
demonstrate the feasibility and superior properties of on-chip transmission line
interconnects, we havedesigned and fabricated a test chip carrying a 5 mm long
globalcommunicationlink. Measurementsshowthatwecanachieve3Gb/s/wire
overthe5mmlong,repeaterlesson-chipbusimplementedinastandard0.18(cid:22)m
CMOS process, achievinga signalvelocityof 1/3 of the velocityof lightin vac-
uum.
To manage the problems due to global wire delays, we describe and imple-
mentaSynchronousLatencyInsensitiveDesign(SLID)scheme,basedonsource-
synchronous data transfer between blocks and data re-timing at the receiving
block. The SLID-technique not only mitigates unknown global wire delays, but
also removes the need for controlling global clock skew. The high-performance
and high robustness capability of the SLID-method is practically demonstrated
through a successful implementation of a SLID-based, 5.4 mm long, on-chip
globalbus,supporting3Gb/s/wireanddynamicallyaccepting(cid:6)2clockcyclesof
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data-clockskew,inastandard0.18(cid:22)mCMOSprocess.
In the context of technology scaling, there is a tendency for interconnects to
dominatechip power dissipationdue to their large total capacitance. In this the-
sis we address the problem of interconnect power dissipation by proposing and
analyzing a transition-energy cost model aimed for efficient power estimation of
performance-critical buses. The model, which includes properties that closely
capture effects present in high-performance VLSI buses, can be used to more
accurately determine the energy benefits of e.g. transition coding of bus topolo-
gies. Wefurthershowapoweroptimizationschemebasedonappropriatechoice
of reduced voltage swing of the interconnect and scaling of receiver amplifier.
Finally,thepowersavingimpactofswingreductionincombinationwithasense-
amplifyingflip-flopreceiverisshownonamicroprocessorcachebusarchitecture
usedinindustry.
Preface
ThisPh.D.thesispresentstheresultsofmyresearchduringtheperiodfromApril
2001toDecember2005attheElectronicDevicesgroup,DepartmentofElectrical
Engineering, Linköping University, Sweden. The following papers are included
inthethesis:
(cid:15) Paper1: PeterCaputaandChristerSvensson,“Low-Power,Low-Latency
Global Interconnect”, in Proceedings of the IEEE ASIC/SOC Conference,
pp.394-398,Rochester,USA,September2002.
(cid:15) Paper 2: ChristerSvensson and Peter Caputa, “High Bandwidth, Low-
Latency Global Interconnect”, in VLSI Circuits and Systems, Proceedings
oftheSPIE,vol.5117,pp.126-134,GranCanaria,Spain,May2003.
(cid:15) Paper3: PeterCaputa,MarkA.Anders,ChristerSvensson,RamK.
Krishnamurthy,andShekharBorkar,“ALow-swingSingle-endedL1Cache
Bus Technique for Sub-90 nm Technologies”, in Proceedings of the Euro-
peanSolid-StateCircuitsConference,pp.475-477,Leuven,Belgium,
September2004.
(cid:15) Paper4: PeterCaputa,HenrikFredriksson,MartinHansson,Stefan
Andersson, AtilaAlvandpour, and ChristerSvensson, “An Extended Tran-
sitionEnergy Cost Model for Buses in Deep Submicron Technologies”, in
ProceedingsofthePowerandTimingModeling,OptimizationandSimula-
tionConference,pp.849-858,Santorini,Greece,September2004.
(cid:15) Paper5: Peter Caputa, AtilaAlvandpour, andChristerSvensson, “High-
SpeedOn-ChipInterconnectModelingforCircuitSimulation”,inProceed-
ings of the Norchip Conference, pp.143-146, Oslo, Norway, November
2004.
(cid:15) Paper6: PeterCaputaandChristerSvensson,“Well-BehavedGlobalOn-
Chip Interconnect”, in IEEE Transactions on Circuits and Systems Part I:
RegularPapers,vol.52,issue2,pp.318-323,February2005.
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(cid:15) Paper7: PeterCaputaandChristerSvensson,“A3Gb/s/wireGlobalOn-
ChipBuswithNearVelocity-of-LightLatency”,tobepresentedattheVLSI
Design2006Conference,Hyderabad,India,January2006.
(cid:15) Paper8: RebeccaKällsten,PeterCaputa,andChristerSvensson,“Capac-
itiveCrosstalkEffectsonOn-ChipInterconnectLatenciesandData-Rates”,
in Proceedings of the Norchip Conference, pp.281-284, Oulu, Finland,
November2005.
(cid:15) Paper 9: Peter Caputa and ChristerSvensson, “An On-Chip Delay- and
Skew-Insensitive Multi-Cycle Communication Scheme”, to be presented
at the International Solid-State Circuits Conference 2006, San Francisco,
USA,February2006.
I have also been involved in research work, which has generated the following
papersfallingoutsidethescopeofthisthesis:
(cid:15) StefanAndersson,PeterCaputa,andChristerSvensson,“ATuned,Induc-
torless,RecursiveFilterinCMOS”, inProceedingsoftheEuropeanSolid-
StateCircuitsConference,pp.351-354,Florence,Italy,September2002.
(cid:15) AtilaAlvandpour,RamK.Krishnamurthy,andPeterCaputa,“High-
performanceandLow-voltageDatapathandInterconnectDesignChallenges”,
tutorialintheIEEEMediterraneanElectrotechnicalConference,Dubrovnik,
Croatia,May2004.
Contributions
Themaincontributionsofthisdissertationareasfollows:
(cid:15) Acomprehensiveanalysisshowingthattheintrinsiclimitationsofelectrical
on-chip interconnects can be overcome by utilizationof transmissionline-
stylewires.
(cid:15) AsuccessfulCMOSimplementationofaglobalcommunicationlinkshow-
ing the feasibility of transmission line-style interconnects achieving near
velocity-of-lightdelayandhighdatarates.
(cid:15) Motivating the use of a Synchronous Latency Insensitive Design (SLID)
schemeforintegratedcircuitsaimedatmanagingthetimingproblemscaused
byunknownon-chipglobalclockskewandwiredelays. Thisincludesval-
idationofthetechniquebymeasurementsoffabricatedsilicon.
(cid:15) A bus transition-energycost modelincludingcapacitances related to inter-
connectinter-layercouplingandtheinternalnodesofarealisticmulti-stage
transmitter-propertieswhichwerenottreatedinpreviousmodels.
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Abbreviations
AC AlternatingCurrent
AR AspectRatio
ASIC Application-SpecificIntegratedCircuit
CAD Computer-AidedDesign
CMOS ComplementaryMetal-Oxide-Semiconductor
DC DirectCurrent
DSM DeepSubMicron
FIFO FirstInFirstOut
GALS GloballyAsynchronousLocallySynchronous
IC IntegratedCircuit
IEEE InstituteofElectricalandElectronicsEngineering
ILD Inter-LayerDielectric
ISI InterSymbolInterference
ITRS InternationalTechnologyRoadmapforSemiconductors
LID LatencyInsensitiveDesign
MOSFET Metal-Oxide-SemiconductorField-EffectTransistor
NMOS N-channelMetal-Oxide-Semiconductor
NoC Network-on-Chip
PCB PrintedCircuitBoard
PMOS P-channelMetal-Oxide-Semiconductor
RC Resistance-Capacitance
RF Radio-Frequency
RLC Resistance-Inductance-Capacitance
Rx Receiver
SLID SynchronousLatencyInsensitiveDesign
SoC System-on-Chip
Tx Transmitter
VLSI VeryLargeScaleIntegration
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