From Variability-Tolerance to Approximate Computing in Parallel Computing Architectures

267 Pages·2015·8.43 MB·English

UNIVERSITYOFCALIFORNIA,SANDIEGO
FromVariability-TolerancetoApproximateComputinginParallelComputing
Architectures
Adissertationsubmittedinpartialsatisfactionofthe
requirementsforthedegreeofDoctorofPhilosophy
in
ComputerScience(ComputerEngineering)
by
AbbasRahimi
Committeeincharge:
ProfessorRajeshK.Gupta,Chair
ProfessorChungKuanCheng
ProfessorRanjitJhala
ProfessorTruongNguyen
ProfessorDeanTullsen
2015
Copyright
AbbasRahimi,2015
Allrightsreserved.
TheDissertationofAbbasRahimiisapprovedandisacceptableinquality
andformforpublicationonmicrofilmandelectronically:
Chair
UniversityofCalifornia,SanDiego
2015
iii
DEDICATION
Tomyparentswitheverlastinggratitude
iv
EPIGRAPH
Thestrongestofallwarriorsarethesetwo–TimeandPatience.
LeoTolstoy,WarandPeace,1869
v
TABLEOFCONTENTS
SignaturePage........................................................ iii
Dedication ........................................................... iv
Epigraph............................................................. v
TableofContents ..................................................... vi
ListofFigures ........................................................ x
ListofTables ......................................................... xv
Acknowledgements.................................................... xvi
Vita ................................................................. xix
AbstractoftheDissertation ............................................. xxiv
Chapter1 Introduction ............................................... 1
1.1 SourcesofVariability .......................................... 1
1.2 DelayVariation ............................................... 3
1.3 DissertationOrganizationandContributions ....................... 6
1.3.1 PredictingandPreventingErrors .......................... 11
1.3.2 DetectingandCorrectingErrors........................... 12
1.3.3 AcceptingErrors ....................................... 13
1.3.4 DetectingandCorrectingwithAcceptingErrors ............. 14
Chapter2 Instruction-LevelTolerance .................................. 15
2.1 Introduction .................................................. 15
2.2 EffectofOperatingConditions .................................. 16
2.3 DelayVariationamongPipelineStages ........................... 17
2.4 InstructionCharacterizationMethodologyandExperimentalResults... 20
2.4.1 Gate-LevelSimulation................................... 21
2.4.2 Instruction-LevelDelayVariability ........................ 22
2.4.3 LessIntrusiveVariation-TolerantTechnique ................. 24
2.4.4 PowerVariability ....................................... 25
2.5 ChapterSummary ............................................. 26
Chapter3 Sequence-LevelTolerance ................................... 27
3.1 Introduction .................................................. 28
3.2 PVTVariations................................................ 29
3.2.1 ConventionalStaticTimingAnalysis....................... 32
vi
3.2.2 Variation-AwareStatisticalSTA ........................... 35
3.3 Error-TolerantApplications ..................................... 36
3.3.1 AnalysisofAdaptiveGuardbandingforProbabilisticApplications 37
3.4 Error-IntolerantApplications .................................... 40
3.4.1 Sequence-LevelVulnerability(SLV) ....................... 40
3.4.2 SLVCharacterization.................................... 42
3.5 AdaptiveGuardbanding ........................................ 47
3.6 ExperimentalResults .......................................... 50
3.6.1 EffectivenessofAdaptiveGuardbanding.................... 52
3.6.2 OverheadofAdaptiveGuardbanding....................... 59
3.7 ChapterSummary ............................................. 60
Chapter4 Procedure-LevelTolerance ................................... 61
4.1 Introduction .................................................. 61
4.2 Variation-TolerantProcessorClustersArchitecture .................. 62
4.2.1 Variation-AwareVDD-Hopping ........................... 64
4.3 ProcedureHoppingforDynamicIR-Drop ......................... 66
4.3.1 SupportingIntra-ClusterProcedureHopping ................ 68
4.4 CharacterizationofPLVtoDynamicOperatingConditions........... 71
4.5 ExperimentalResults .......................................... 74
4.5.1 CostofProcedureHopping............................... 76
4.6 ChapterSummary ............................................. 78
Chapter5 Kernel-LevelTolerance...................................... 79
5.1 Introduction .................................................. 80
5.2 Device-LevelNBTIModel...................................... 81
5.3 GP-GPUArchitecture .......................................... 83
5.3.1 GP-GPUWorkloadDistribution........................... 84
5.4 Aging-AwareCompilation ...................................... 86
5.4.1 Observability: AgingSensors ............................. 87
5.4.2 Prediction: WearoutEstimationModule .................... 89
5.4.3 Controllability: UniformSlotAssignment .................. 90
5.5 ExperimentalResults .......................................... 92
5.6 ChapterSummary ............................................. 95
Chapter6 Work-UnitTolerance........................................ 97
6.1 Introduction .................................................. 98
6.2 ArchitecturalSupportforVOMP................................. 101
6.3 Work-UnitVulnerabilityandVOMPWork-Sharing ................. 104
6.3.1 Intra-andInter-CornerWUV ............................. 107
6.3.2 OnlineWUVCharacterization ............................ 114
6.4 VOMPSchedulers............................................. 117
6.4.1 Variation-AwareTaskScheduling(VATS)................... 117
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6.4.2 Variation-AwareSectionScheduling(VASS) ................ 121
6.5 ExperimentalResults .......................................... 123
6.5.1 FrameworkSetup ....................................... 123
6.5.2 VOMPResultsforTasking ............................... 125
6.5.3 VOMPResultsforSections .............................. 127
6.6 ChapterSummary ............................................. 128
Chapter7 HierarchicallyFocusedGuardbanding ......................... 130
7.1 Introduction .................................................. 131
7.2 TimingErrorModelforPVTA................................... 132
7.2.1 AnalysisFlowforTimingErrorExtraction.................. 132
7.2.2 ParametricModelFitting................................. 136
7.2.3 TERClassification ...................................... 138
7.2.4 RobustnessofClassification .............................. 139
7.3 RuntimeHierarchicallyFocusedGuardbanding .................... 140
7.3.1 Observability........................................... 142
7.3.2 Controllability.......................................... 143
7.4 ACaseStudyofHFGonGPUs.................................. 146
7.5 ChapterSummary ............................................. 147
Chapter8 ExactMemristiveAssociativeMemory ........................ 149
8.1 Introduction .................................................. 150
8.2 Energy-EfficientGP-GPUs...................................... 153
8.2.1 AssociativeMemristive-BasedComputing .................. 154
8.3 CollaborativeCompilation ...................................... 157
8.3.1 FPUMemristive-basedComputing ........................ 159
8.4 ExperimentalResults .......................................... 161
8.4.1 FPUswithAMMModules ............................... 161
8.4.2 EnergySaving.......................................... 163
8.5 ChapterSummary ............................................. 166
Chapter9 Accuracy-ConfigurableOpenMP.............................. 167
9.1 Introduction .................................................. 168
9.2 ControlledApproximation ...................................... 170
9.3 Accuracy-ConfigurableOpenMPEnvironment ..................... 171
9.3.1 Accuracy-ConfigurableFPUs ............................. 171
9.3.2 OpenMPCompilerExtensionforApproximation ............ 173
9.3.3 RuntimeSupport ....................................... 175
9.3.4 Application-DrivenHardwareFPUSynthesisandOptimization 176
9.4 ExperimentalResults .......................................... 178
9.4.1 Error-TolerantApplications .............................. 180
9.4.2 Error-intolerantApplications ............................. 185
9.5 ChapterSummary ............................................. 188
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Chapter10 ApproximateMemristiveAssociativeMemory .................. 190
10.1 Introduction .................................................. 191
10.2 GPUArchitectureUsingA2M2 Module ........................... 194
10.2.1 SouthernIslandsArchitecture............................. 194
10.2.2 ApproximateAssociativeMemristiveMemoryModule ....... 195
10.3 FrameworktoSupportA2M2 .................................... 200
10.3.1 ExecutionFlow......................................... 200
10.3.2 DesignSpaceforA2M2 .................................. 202
10.4 ExperimentalResults .......................................... 204
10.4.1 ExperimentalSetup ..................................... 204
10.4.2 EnergySavingwithCorrespondingPSNR .................. 206
10.5 ChapterSummary ............................................. 208
Chapter11 SpatialandTemporalMemoization............................ 210
11.1 Introduction .................................................. 211
11.2 SpatialMemoization(ConcurrentInstructionReuse) ................ 213
11.2.1 SingleStrongMultipleWeak(SSMW)Architecture .......... 214
11.2.2 ExperimentalResults .................................... 218
11.3 TemporalMemoization(TemporalInstructionReuse) ............... 220
11.3.1 TemporalMemoizationforErrorRecovery.................. 221
11.3.2 ExperimentalResults .................................... 222
11.4 ChapterSummary ............................................. 222
Chapter12 Outlook................................................... 224
12.1 Domain-SpecificSoftwareResiliency............................. 225
12.1.1 Software .............................................. 225
12.1.2 Architecture ........................................... 226
12.1.3 Circuit ................................................ 226
12.2 Non-VonNeumannMassivelyParallelArchitectures ................ 227
Bibliography ......................................................... 228
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LISTOFFIGURES
Figure1.1. WIDcore-to-coremaximumclockfrequencyvariationfor80cores
onasinglechip[58]. ...................................... 4
Figure1.2. Criticalpathdelaydistributionanditscoefficientofvariation(σ/µ)
for80coresonasinglechip[58]. ........................... 4
Figure1.3. Impact of voltage scaling on gate delay variation due to process
variation[60]............................................. 5
Figure1.4. Taxonomyoftimingerrortoleranceinthisdissertation: abstractions
versusapproaches. ........................................ 7
Figure2.1. Effectofvoltageandtemperaturevariationsonthecriticalpath(ns). 17
Figure2.2. Effectofvoltagevariationonthepipelinestagesat125◦C. ...... 18
Figure2.3. Effectoftemperaturevariationonthenumberoffailedpathsamong
thepipelinestagesat1.10V. ................................ 19
Figure2.4. Theproportionoffailedpathstonon-failedpathsversusclock. .. 20
Figure2.5. Intera-andinter-cornertotalpower(W)variabilityoftheinstruction
classes. ................................................. 25
Figure3.1. Non-uniformslackvariation oftheintegerpipelinestagescaused
byPVTwithcycletimeat0.83ns. ........................... 31
Figure3.2. NumberoffailedpathsofLEON3pipelineusingSTA. ......... 33
Figure3.3. NumberoffailedpathsofTHEIApipelineusingSTA........... 34
Figure3.4. Variation-awareSSTAversustheworst-caseSTA. ............. 35
Figure3.5. Trade-off between the cycle time and the probability of having a
failureintheexecutionstage. ............................... 40
Figure3.6. Intra-cornerSLVtodynamicvariations(∆T=165◦CandV=0.09V);
a: (0.72V,125◦C),b: (0.81V,125◦C),c: (0.81V,-40◦C)........... 45
Figure3.7. ILVandSLVclassificationforintegerSPARCV8ISA. ......... 47
Figure3.8. Methodologyfortheadaptiveguardbanding. .................. 51
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