FPGA Based Accelerators for Financial Applications

288 Pages·2015·8.83 MB·English

by  Christian De Schryver (eds.)

Christian De Schryver Editor
FPGA Based
Accelerators
for Financial
Applications
FPGA Based Accelerators for Financial
Applications

Christian De Schryver
Editor
FPGA Based Accelerators
for Financial Applications
123
Editor
ChristianDeSchryver
UniversityofKaiserslautern
Kaiserslautern,Germany
ISBN978-3-319-15406-0 ISBN978-3-319-15407-7 (eBook)
DOI10.1007/978-3-319-15407-7
LibraryofCongressControlNumber:2015940116
SpringerChamHeidelbergNewYorkDordrechtLondon
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Preface from the Editor
1 TheNeed for ReconfigurableComputingSystems
inFinance
ThefinancesectorisoneofmostprominentusersofHighPerformanceComputing
(HPC) facilities. It is not only due to the aftermath of the financial crisis in
2008 that the computational demands have surged over the last years but due to
increasingregulations(e.g.,BaselIIIandSolvencyII)andreportingrequirements.
Institutesareforcedtodelivervaluationandrisksimulationresultstointernalrisk
managementdepartmentsandexternalregulatoryauthoritiesfrequently[2,16,17].
Oneimportantbottleneckinmanyinvestmentandriskmanagementcalculations
is the pricing of exotic derivativesin appropriatemarket models [2]. However, in
manyofthesecases,no(semi)closed-formpricingformulasexist,andtheevaluation
is carried out by applying numerical approximations. In most cases, calculating
thosenumbersforacompleteportfoliocanbeverycomputeintensiveandcanlast
hours to days on state-of-the-art compute clusters with thousands of cores [17].
Theincreasingcomplexityoftheunderlyingmarketmodelsandfinancialproducts
makes this situation even worse [2, 5, 6, 8]. In addition, the progress in online
applicationslikenewsaggregationandanalysis[9]andthecompetitioninthefield
oflow-latencyandHigh-FrequencyTrading(HFT)requirenewtechnologiestokeep
trackwiththeoperationalandmarketdemands.
DatacentersandHPCingeneralarecurrentlyfacingamassiveenergyproblem
[2,3].Inparticular,thisalsoholdsforfinancialapplications:Theenergyneededfor
portfoliopricingisimmenseandliesintherangeofseveralmegawattsforasingle
average-sizedinstitutetoday[17].Alreadyin2008theavailablepowerforCanary
Wharf,thefinancialdistrictofLondon,hadtobelimitedtoensureareliablesupply
fortheOlympicGamesin2012[15].Inaddition,energycostsalsoforcefinancial
institutestolookintoalternativewaysofobtainingsufficientcomputationalpower
atloweroperatingcosts[16].
Two fundamental design principles for high-performance and energy-efficient
computing appliances are the shifts to high data locality with minimum data
v
vi PrefacefromtheEditor
movements and to heterogeneous computing platforms that integrate dedicated
and specialized hardware accelerators. The performance of battery-driven mobile
devices we experience today is grounded in these concepts. Nowadays, the need
for heterogeneity is widely acknowledged in the HPC domain as well [2, 3].
Nevertheless, the vast majority of current data centers and in-house computing
systemsisstillbasedongeneral-purposeCentralProcessingUnits(CPUs),Graphics
Processor Units (GPUs), or Intel Xeon Phi processors. The reason is that those
architectures are tailored to providing a high flexibility on application level, but
atthecostoflowenergyefficiency.
Dedicated Application Specific Integrated Circuit (ASIC) accelerator chips
achieve the optimal performance and energy efficiency. However, ASICs come
withsomesignificantdrawbacksregardingtheiruseinsupercomputingsystemsin
general:
1. TheNon-recurringEngineering(NRE)andfixedmanufacturingcostsforcustom
ASICs are in the range of several 100 million USD for state-of-the-art 28nm
processes [10]. This means that the cost per unit is enormous for low volume
productionandthereforeeconomicallyunfeasible.
2. Manufactured ASICs are unalterably wired circuits and can therefore only
providetheflexibilitythathasbeenincorporatedintotheirarchitectureatdesign
time. Changing their functionality or adding additional features beyond those
capabilitieswouldrequireareplacementofthehardwarewithupdatedversions.
3. The design effortand thereforealso the Time to Market(TTM) is in the range
ofmonthstoyearsforASICdevelopment.However,inparticularinthefinance
domain,itcanbenecessarytoimplementnewproductsoralgorithmsveryfast.
DesigninganewASICforthisisprobablynotviable.
In contrast to ASICs, reconfigurable devices like Field Programmable Gate
Arrays (FPGAs) can be reprogrammed without limit and can change their func-
tionality even while the system is running. Therefore, they are a very promising
technology for integrating dedicated hardware accelerators in existing CPU- and
GPU-basedcomputingsystems,resultinginso-calledHighPerformanceReconfig-
urableComputing(HPRC)architectures[14].
FPGAs have already shown to outperform CPU- and GPU-only architectures
withrespecttospeedandenergyefficiencybyfarforfinancialapplications[1,2,12].
Firstattemptsto use reconfigurabletechnologyin practiceare made,forexample,
byJ.P.Morgan[4]orDeutscheBank[11].
However, the use of FPGAs still comes with a lot of challenges. For example,
nostandarddesignandintegrationflowsexistuptonowthatmakethistechnology
available to software and algorithmic engineers right away. First approachessuch
as the Maxeler systems,1 the MathWorks HDL Coder [13], the Altera OpenCL
flow[7],orthe XilinxSDAccelapproach[18] aremovingintotherightdirection,
but still requirefundamentalknow-howabouthardwaredesign in orderto end up
1http://www.maxeler.com
PrefacefromtheEditor vii
with powerful accelerator solutions. Hybrid devices like the recent Xilinx Zynq
All Programmable system on chips (SoCs) combine standard CPU cores with a
reconfigurableFPGApartandthusenablecompletelynewsystemarchitecturesalso
intheHPRCdomain.Thisbooksummarizesthemainideasandconceptsrequired
forsuccessfullyintegratingFPGAsintofinancialcomputingsystems.
2 IntendedAudienceandPurposeof ThisBook
When I started my work as a researcher in the field of accelerating financial
applications with FPGAs in 2010 at the University of Kaiserslautern, I found
myself in a place where interdisciplinary collaboration between engineers and
mathematicianswasnotonlyabuzzword,buthadalongandlivedtradition.Itwas
notonlyestablishedthroughinformalcooperationprojectsbetweenthedepartments
andresearchgroupswithintheuniversityitself,butalsomaterialized,forexample,
in the Center for Mathematical and Computational Modelling ((CM)2). (CM)2 is
a research center funded by the German state Rhineland-Palatinate with the aim
of showing that mathematics and computer science represent a technologythat is
essentialto engineersand naturalscientists and thatwill help advanceprogressin
relevantareas.2IhavecarriedoutmyfirstworksasamemberoftheMicroelectronic
Systems Design Research Group headed by Prof. Norbert Wehn in the context
of the very successful (CM)2 project “Hardware assisted Acceleration for Monte
CarloSimulationsinFinancialMathematicswithaparticularEmphasisonOption
Pricing(HOPP).”Asoneoutcomeof(CM)2,theDeutscheForschungsgemeinschaft
(DFG)hasdecidedtoimplementa newresearchtraininggroup(RTG)1932titled
“StochasticModelsforInnovationsintheEngineeringSciences”attheUniversity
ofKaiserslauternfortheperiodApril2014–September2018(seePrefacefromProf.
RalfKorn,speakeroftheRTG1932).
In addition to the successful networking within the university, Kaiserslautern
is a famous location for fruitful cooperations between companies and institutes
in the fields of engineering and mathematics in general. Particularly active in the
fieldoffinancialmathematicsistheFraunhoferInstituteforIndustrialMathematics
(ITWM),3awell-reputedapplication-orientedresearchinstitutionwiththemission
of applying the latest mathematical findings from research to overcome practical
challenges from industry. It is located only a short distance from the university
campus.
Despite the beneficial circumstances, one of my first discoveries was that
it was quite hard to get an overview about what is already going on in the
field “accelerating financial applications with FPGAs.” The reason is that we
areenteringa stronglyinterdisciplinaryenvironmentcomprisinghardwaredesign,
2http://cmcm.uni-kl.de/en
3http://www.itwm.fraunhofer.de/en/departments/financial-mathematics.html
viii PrefacefromtheEditor
financial mathematics, computational stochastics, benchmarking, HPC, and soft-
ware engineering. Although many particular topics had already been investigated
in detail, their impact in the context of “accelerating financial applications with
reconfigurablearchitectures”wasnotalwaysobvious.Inaddition,uptonowthere
isnoaccessibletextbookavailablethatcoversallimportantaspectsofusingFPGAs
forfinancialapplications.
My mainmotivationto comeupwith thisbookis exactlyto close thisgapand
tomakeiteasierforreaderstoseetheglobalpicturerequiredtoidentifythecritical
points from all cross-disciplinary viewpoints. The book summarizes the current
challengesinfinanceandthereforejustifiestheneedsfornewcomputingconcepts
including FPGA-based accelerators, both for readers from finance business and
research.It coversthe most promisingstrategiesfor acceleratingvariousfinancial
applicationsknown today and illustrates that real interdisciplinary approachesare
crucialtocomeupwith powerfulandefficientcomputingsystemsforthoseinthe
end.
For people new to or particularlyinterested in this topic, the book summarizes
thestate-of-the-artworkandthereforeshouldactasaguidethroughallthevarious
approachesandideas.Ithelpsreadersfromtheacademicdomaintogetanoverview
aboutpossibleresearchfieldsandpointsoutthoseareaswherefurtherinvestigations
are neededto make FPGAs accessible for people from practice.For practitioners,
the book highlights the most important concepts and the latest findings from
research and illustrates how those can help to identify and overcome bottlenecks
in current systems. Quants and algorithmic developers will get insights into the
technological effects that may limit their implementations in the end and how to
overcome those. For managers and administrators in the Information Technology
(IT) domain, the book gives answers about how to integrate FPGAs into existing
systemsandhowtoensureflexibilityandmaintainabilityovertime.
3 OutlineandOrganization ofthe Book
A big obstacle for researchers is the fact that it is generally very hard to get
access to the real technological challenges that financial institutes are facing in
daily business. My experience is that this information can only be obtained in
face-to-face discussions with practitionersand will vastly differ from companyto
company. Chapter 1 by Desmettre and Korn therefore highlights the 10 biggest
challenges in the finance business from a viewpoint of financial mathematics and
riskmanagement.
One particular computationally challenging task in finance is calibrating the
market models against the market. Chapter 2 by Sayer and Wenzel outlines the
calibrationprocessanddistillsthemostcriticalpointsinthisprocess.Furthermore,
itshowswhichstepsinthecalibrationprocessarethemainlimitingfactorsandhow
theycanbetackledtospeedupthecalibrationprocessingeneral.
PrefacefromtheEditor ix
In Chap.3, Delivorias motivates the use of FPGAs for pricing tasks by giving
throughputnumbersforCPU, GPU, and FPGA systems. He considerspricepaths
generatedintheHestonmarketmodelandcomparestheruntimeoverallplatforms.
Fairly comparing various platforms on application level is a nontrivial task,
in particular when different algorithms are used. Chapter 4 by De Schryver and
Noguiera introduces a generic benchmark approach together with appropriate
metrics that can be used to characterize the performance and energy efficiency
of (heterogeneous)systems independentof the underlying technology and imple-
mentedalgorithm.
High-Level Synthesis (HLS) is currently moving into productive hardware
designs and seems to be one of the most promising approaches to make FPGAs
accessible to algorithm and software developers. In Chap.5, Inggs, Fleming,
Thomas, and Luk demonstrate the current performance of HLS for financial
applicationswithanoptionpricingcasestudy.
In addition to the design of the hardware accelerator architecture itself, its
integrationintoexistingcomputingsystemisacrucialpointthatneedstobesolved.
Chapter 6 by Sadri, De Schryver, and Wehn introduces the basics of Peripheral
ComponentInterconnectExpress(PCIe)andAdvancedeXtensibleInterface(AXI),
two of the most advanced interfaces currently used in HPC and System on Chip
(SoC)architectures.ForthehybridXilinxZynqdevicethatcomeswithaCPUand
anFPGApartitpointsoutpossiblepitfallsandhowtheycanbeovercomewhenever
FPGAsneedtobeattachedtoexistinghostsystemsoverPCIe.
Path-dependent options are particularly challenging for acceleration with ded-
icated architectures. The reason is that the payoff of those products needs to be
evaluatedateveryconsideredpointintimeuntilthematurity.ForAmericanoptions,
Varela,Brugger,Tang, Wehn,and Kornillustrate in Chap.7 how a pricingsystem
forpath-dependentoptionscanbeefficientlyimplementedonahybridCPU/FPGA
system.
OnemajorbenefitofFPGAsistheirreconfigurabilityandthereforetheflexibility
theycanprovideonceintegratedintoHPCcomputingsystems.However,currently
thereisnostandardmethodologyonhowtoexploitthisreconfigurabilityefficiently
at runtime. In Chap.8, Brugger, De Schryver, and Wehn propose HyPER, a
framework for efficient option pricer implementations on generic hybrid systems
consisting of CPU and FPGA parts. They describe their approach in detail and
showthatHyPERis3.4×fasterand36×morepowerefficientthanahighlytuned
softwarereferenceonanIntelCorei5CPU.
While on CPUs and GPUs the hardware and therefore the available data types
arefixed,FPGAsgivecompletefreedomtotheuseraboutwhichprecisionandbit
widthsshouldbeusedineachstageofthearchitecture.Thisopensupacompletely
newdegreeoffreedomandalsoheavilyinfluencesthecostsofavailablealgorithms
wheneverimplementedon FPGAs. Chapter 9 by Omland, Hefter,Ritter, Brugger,
De Schryver, Wehn, and Kostiuk outlines this issue and shows how so-called
mixed-precisionsystems can be designed withoutlosing any accuracyof the final
computationresults.