Flexible Fault Tolerance Using the ARTEMIS Reconfigurable

24 Pages·2007·8.15 MB·English

Aerospace Data Storage and Processing Systems
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Ian A. Troxel
Matthew Fehringer
Michael T. Chenoweth
SEAKR Engineering, Inc.
Military and Aerospace FPGA and Applications (MAFA) Meeting
Palm Beach, FL
November 27-29, 2007
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Aerospace Data Storage and Processing Systems
o “Responsive Space refers to the ability to rapidly achieve a specific
objective through the use of space with rapidly being the operative
word. The AFRL Office of Force Transformation suggested that the
goal for fielding a new payload is weeks and months and not
decades.” [1]
o Tactical Satellite (TacSat) program building competency to achieve
the Responsive Space challenge [2]
• Joint AFRL and NRL demonstration program
• Goal to develop capability to field inexpensive space systems in time of
crisis to augment and reconstitute existing capabilities or perform
entirely new tactical theater support missions
• Key success criteria include
– Develop low cost ($20 million or less) mission-specific spacecraft
– Rapid deployment with on orbit activation within six days of call up
– Provide between six to twelve months of reliable mission operations
[1] Lanza, et. al., “Responsive Space Through Adaptive Avionics, Responsive Space Conference, Los Angeles, CA, April 19-22, 2004.
[2] J. Raymond, et. al., “A TacSatUpdate and the ORS/JWS Standard Bus,” Responsive Space Conference, Los Angeles, CA, April 25-28, 2006.
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Aerospace Data Storage and Processing Systems
Spacecraft:
3. Collect Image
Dedicated Space Capabilities Direct
4. Process Product
to Operational and Tactical Levels
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Data Products
6. Receive Product
Tactical
Ground
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Aerospace Data Storage and Processing Systems
o Geo-registered false color HSI
• Supports GeoPaintTM display
o Target cue reports (text data)
• Date, time, filter ID
• Scan, frame, pixel indices
• Lat,Lon and UTM geolocation
o Target chips
• ROI centered on detection
• Georegistered and fused
false-color HSI and HRI
• Target spectra
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Aerospace Data Storage and Processing Systems
oARTEMIS designed for Responsive Space
• Low cost
• High Performance
• Rapid deployment through adaptability
oKey System Development Requirements
• Scalable processing from 9 to over 400 GFLOPS
• Reconfigurable, on-orbit
• Support Multi-Terabit Data Storage
• Usage of open standards
• SEE Tolerant system
• Flexible I/O architecture
• Provide user interface for rapid development
oThe Application Independent Processor fulfills ARTEMIS goals
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Aerospace Data Storage and Processing Systems
o Space Qualified On-Board Processor System o DC/DC – 82% efficient supply
• Based on both scalar and reconfigurable o SWaP (estimate)
computing
• Mass: EM 18 lbs (no conformal coat)
• AFRL TacSat 3 flight program
• Size: 7.82H x 11.41W x 10.0D inches
o (Up to two) Reconfigurable Computer(s)
• Power: 40 Watts (EM measured)
• V4 based RCC with 256 MB DDRII SDRAM per
• -10 to +50°C
Coprocessor (COP)
• High speed SERDES backplane bus
• Over 450,000 logic cells (500 MHz)
• 15.6 Mb of embedded block RAM (500 MHz)
• 288 18x18 multipliers (500 MHz)
• 20 Watts
o G4 PowerPC SBC
• 600 DMIPs, 1.2 GFLOP
• VxWorks Based
• Gigabit Ethernet and Spacewire
• 16 Watts
o Memory and I/O Mezzanine (ARTEMIS
Personality Mezzanine)
• 16 GBytes flash memory
• Camera link, analog, digital
o Payload Power Switching
• 28V switched power to payload
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Aerospace Data Storage and Processing Systems
Shown in the
TacSat3 ARTEMIS
configuration
GPS CameraLink Analog Focus GigE Switched
1 pps 2 ports Position Mechanism PMC 28V
Power
UPS
Supply
Spare Slot
Additional RA-RCC
Memory Cards
I/O Cards
RA-RCC#1 G4 PowerPC
Power Planes 3.3,5
28 Volts
Spacewire
PCI Bus A
4 bit SERDES
Backplane
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Aerospace Data Storage and Processing Systems
o I/O
o 6u cPCI (32b/33MHz) – PCI
• Spacewire (2 ports)
o Flash
• RS422 (2 ports)
• 512 Mbytes user-available memory
• Temperature Sensor
• Reed Solomon EDAC with Single symbol correct
• Emulator Signals
• 56Mbytes/sec for single beat transfers
• Ethernet via PMC Mezzanine
o SDRAM
• GPIO (16 bits input, 16 bits output)
• 256Mbytes user-available with full chip correct
• Boot-status and error indication (4 bits)
EDAC
• Mode register refresh on command
o EEPROM
• 128kbytes user-available with Hamming EDAC
• Single bit correct & Double bit detect Cache
o Processor Cache
• 32kbyte Level 1
• 256kbyte Level 2
o PMC
• Local PCI bus (PCI/PCI)
• Ethernet signals routed to backplane on J3
o Mass and Power
• Mass: 0.55 kg, 1.22 lbs
G4 Prototype cPCI
• Power: 3.3V/1A, 5V/2A, +12V/0.135A, -12V/0.014A
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Aerospace Data Storage and Processing Systems
o Devices require low voltage
and high current.
o Must use Point Of Load POL
power supplies for proper
regulation
o Developed Radiation tolerant
POL mezzanine
• Programmable voltage down
to 1.0V at 12A
• 85% efficiency
• Mezzanine card for design
reuse and flexibility
RA-RCC Back View
POL Power
Supply
POL DC/DC Converter Mezz
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Aerospace Data Storage and Processing Systems
256 Mbytes
256 Mbytes
Reed Solomon Protected
o 3 V4LX160 FPGAs PPooinint to of fL Looadad Reed Solomon Protected
DDR-II Memory
DC/DC Converter DDR-II Memory
o TID tolerant to >40krad DC/DC Converter
• Higher levels available
o 256MBytes DDRII SDRAM
per FPGA
o 170 user defined I/O per
FPGA via high-speed Mezz
o Extended 6U cPCI
o Symmetrical Design
o High speed serial I/O
o 62 configuration files stored
on-board
o Supports full device level Xilinx V4 LX160
Xilinx V4 LX160
TMR with external majority
voting
o Autonomous FPGA
scrubbing with SEFI
protection and recovery
o High Speed Serial
Backplane Interface
Xilinx to Actel Adaptor
o 2.6 lbs with mezzanine Xilinx to Actel Adaptor
Allows Xilinx to be used in 624 pin 4 Gbits of TMR Flash
Allows Xilinx to be used in 624 pin 4 Gbits of TMR Flash
o 9.2 x 7.3 x 1.43” Actel RTAX2000 PCB footprint HHigighh S Sppeeeded
Actel RTAX2000 PCB footprint
Serial Backplane
Serial Backplane
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