Table Of Content

Fullyy Deppleted SOI Technologgies Bich-Yen Nguyen AAcckknnoowwlleeddggeemmeennttss SOITEC Team: IBM Team: • Jean-Michel Bidault • Kangguo Cheng • NNiiccoollaass DDaavvaall • AAllii KKhhaakkiiffiirroooozz • Frederic Allibert • Bruce Doris • Ludovic Ecarnot • Ghavam Shahidi • Konstantin Bourdelle • Walter Schwarzenbach STM Team: • Mariam Sadaka • Qing Liu • Phuong Nguyen • Franck Arnaud • CCaarrllooss MMaazzuurree • NNiiccoollaass PPllaanneess • Olivier Bonnin • Giorgio Cesana • Christophe Malevillle • JJuussttiinn WWaanngg GGlloobbaall FFoouunnddrriieess :: CEA/Leti Team: • Scott Luning • Olivier Weber • Francois Andrieu • Maul Vinet • Olivier Faynot MOS-AK/GSA Workshop, April 11-12, 2013 2 • CMOS Landscape Beyond 28nm Node • Value propositions of the Planar Fully Depletet SOI Technology • Performance and Power Benchmarking • FFDDSSOOII DDeevviiccee aanndd SSuubbssttrraattee RRooaaddmmaapp • Summary MOS-AK/GSA Workshop, April 11-12, 2013 CMOS Landscape Beyond 28nm MOS-AK/GSA Workshop, April 11-12, 2013 4 Challenges of Continued CMOS Scaling Source: IBM, T.C. Chen, ISSCC 2006 •• IInnccrreeaasseedd ssttaannddbbyy ppoowweerr ddiissssiippaattiioonn • Amplified V variability th ⇒⇒IImmppaacctt YYiieelldd ⇒Limit Vdd scaling 5 MOS-AK/GSA Workshop, April 11-12, 2013 Leakage Power is still a Major Issue Despite the UUssee ooff HHii-KK DDiieelleeccttrriicc High-K/Metal Gate SSttaacckk SiON/Poly Gate Stack Source: IBS MOS-AK/GSA Workshop, April 11-12, 2013 6 New Device Architectures 2003 2005 2007 2009 2011 90nm 45 nm 22nm 65nm 32nm Strained Silicon Introduction of New High-K / Metal Gate Materials IInnttrroodduccttiioonn ooff NNeew FFulllly DDepllettedd Device Architecture Devices MOS-AK/GSA Workshop, April 11-12 2013 7 Fully Depleted Technology Landscape Intel IBM STM Foundries – Foundries Foundries 16/14 nm MOS-AK/GSA Workshop, April 11-12, 2013 Value Propositions of the Planar FFuullllyy DDeepplleetteedd SSOOII TTeecchhnnoollooggyy MOS-AK/GSA Workshop, April 11-12, 2013 9 Alternate FD Device Architectures: Planar FDSOI or Vertical Multi-Gate FinFET-SOI Minimum Design G Max DDiissrruuppttiioonn GG D scallabbiilliitty S S D S G D Buried OX Bulk Si Bulk Si BBuurriieedd ooxxiiddee Conventional Planar Planar Single-or Vertical Multiple-Gate Bulk Transistor double Gate FDSOI FinFET SOI MOS-AK/GSA Workshop, April 11-12, 2013

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Apr 12, 2013 Value propositions of the Planar Fully Depletet SOI. Technology. • Performance and Power Benchmarking. • FDSOI Device and Substrate

FDSOI Devices Bentchmarking - MOS-AK PDF

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Apr 12, 2013 Value propositions of the Planar Fully Depletet SOI. Technology. • Performance and Power Benchmarking. • FDSOI Device and Substrate

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Publication Year:	2013
Pages:	42
Language:	English
File Size:	6.06
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