Table Of ContentFAULT COVERING PROBLEMS IN
RECONFIGURABLE VLSI
SYSTEMS
THE KLUWER INTERNATIONAL SERIES
IN ENGINEERING AND COMPUTER SCIENCE
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DIGITAL SIGNAL PROCESSING
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FAULT COVERING PROBLEMS IN
RECONFIGURABLE VLSI
SYSTEMS
by
Ran Libeskind-Hadas
University ofI llinois, Urbana-Champaign
Nany Hasan
IBM Corporation
Jason Cong
University of Califomia, Los Angeles
Philip K. McKinley
Michigan State University
C. L. Liu
University of Illinois, Urbana-Champaign
SPRINGER SCIENCE+BUSINESS MEDIA, LLC
Library of Congress Cataloging.in.Publication Data
Fault covering problems in reconfigurable VLSI systems / by Ran
Libeskind·Hadas ... [et al.].
p. cm.·· (The Kluwer international series in engineering and
computer sciences. VLSI, computer architecture, and digital signal
processing)
Includes bibliographieal references and index.
ISBN 978-1-4613-6606-5 ISBN 978-1-4615-3614-7 (eBook)
DOI 10.1007/978-1-4615-3614-7
1. Integrated circuits--Very large scale integration--Design and
construction·-Data processing. 2. Integrated circuits--Wafer-scale
integration-.Design and construction--Data processing. 3. Fault
-tolerant computing. I. Libeskind-Hadas, Ran. 11. Series.
TK7874.F38 1992
621.39'5-·dc20 92-4369
CIP
Copyright © 1992 Springer Science+Business Media New York
Originally published by Kluwer Academic Publishers,New York in 1992
Softcover reprint ofthe hardcover 1st edition 1992
All rights reserved. No part of this publication may be reproduced, stored in a retrieval
system or transmi tted in any form or by any means, mechanical, photo-copying, recording,
or otherwise, without the prior written permission of the publisher, Springer
Science+Business Media, LLC.
Printed Oll acid-free paper.
This book is dedicated to the Department of Computer Science at
the University of Illinois at Urbana-Champaign.
CONTENTS
Preface xiii
1 An Overview 1
1.1 Introduction 1
1.2 The Embedding Approach 3
1.3 The Covering Approach 7
1.3.1 Previous Work 7
1.3.2 Physical Implementation Issues
in Reconfigurable Design 9
1.4 Overview of Remaining Chapters 15
2 Fault Covers in Rectangular Arrays 19
2.1 Introduction 19
2.2 Admissible Assignments 21
2.3 The Feasible Minimum Cover Problem 24
2.3.1 Critical Sets 25
2.3.2 An Exhaustive Search Algorithm for the
Feasible Minimum Cover Problem 33
2.3.3 Experimental Results 38
2.4 The Feasible Cover Problem 39
2.4.1 Excess-k Critical Sets 39
2.4.2 Experimental Results 45
2.5 Two Reconfiguration Problems 47
2.5.1 Reconfiguration with Shared Spares 49
2.5.2 Reconfiguration of Programmable Logic
Arrays 50
2.6 Summary 54
viii
3 Fault Covers in Heterogeneous and General Arrays 55
3.1 Introduction 55
3.2 Fault Covers in Heterogeneous Arrays 56
3.2.1 The Feasible Cover Problem 58
3.2.2 The Feasible Minimum Cover Problem 62
3.2.3 The Minimum Feasible Cover Problem 64
3.2.4 The Feasible Cover Problem with Multiple
Spare Arrays 71
3.2.5 Applications of the Heterogeneous Array
Model 74
3.3 Fault Covers in General Arrays 76
3.3.1 The Feasible Cover Problem 78
3.3.2 The Feasible Minimum Cover Problem 83
3.3.3 The Minimum Feasible Cover Problem 86
3.4 Summary 89
4 General Formulation of Fault Covering Problems 91
4.1 Introduction 91
4.2 A General Formulation 93
4.3 Illustrative Examples 96
4.4 Integer Linear Programming Approach 100
4.4.1 The General Transformation 101
4.4.2 Experimental Results 105
4.5 Complexity Analysis of Subcases 107
4.5.1 The Definition of Subcases and Their
Complexities 108
4.5.2 Polynomial Time Algorithms 110
4.5.3 NP-Completeness Results 112
4.6 Summary 116
Bibliography 119
Index 129
List of Figures
1.1 A memory chip with spare rows and columns. . . . . .. . 8
1.2 A 2m X 2n memory chip with 2k data bus. . . . . . .. .. 10
1.3 ( a) An m-bit decoder. (b) A 4-bit decoder for the address
0110. . . . . . . . . . . . . . . . . . . . . . . ... . 10. . . .
1.4 A memory chip with spare rows and columns. . . . . . .. 11
1.5 (a) A generic spare row decoder. (b) A 4-bit spare row
decoder reconfigured for the address 0110. . . . . . . . .1.2
1.6 Two different designs allowing the disconnection of a row
containing faulty elements. 13
2.1 A reconfigurable array. . . . 23
2.2 (a) Standard expansion of partial solution. (b) Enlarging
the partial solution with an admissible assignment prior
to expansion. . . . . . . . . . . . . . . . . . . . . 24
2.3 A faulty array and the corresponding critical set. 26
2.4 An array and its bipartite graph representation. . 26
2.5 illustration of Lemma 1. . . . . . . . . . . . . . 29
2.6 Vertex sets used in computation of critical sets. 31
2.7 illustration of Theorem 4. . . . . . . . . . . . . 33
2.8 Example of the Min-Cover algorithm. .. . .. 36
2.9 (a) The graph G and related sets. (b) The graph G( v)
and matching M(v). . . . . . . . . . . . . 42
2.10 Two arrays sharing spare columns. . . . . 49
2.11 A redundant Programmable Logic Array. 51
3.1 A reconfigurable array with multiple types of elements. . 56
3.2 Three faulty heterogeneous arrays. 58
3.3 Multigraph for feasibility problem. . . . . . . . . .. .. 60
x
3.4 Construction of G3 from GI and G2. 68
3.5 Construction of arrays from a graph. 70
3.6 Multiple spare array problem. . . . . 72
3.7 Reconfiguration with shared spares. 75
3.8 Reconfigurable stack of arrays. ... 75
3.9 Example of the general array model. 77
3.10 Construction of array A from arrays AI, ... , At. . 87
4.1 The chip of Example 4.1. ............. 92
4.2 The generalized bipartite graph for Example 4.1. 96
4.3 ( a) A faulty homogeneous array. (b) The corresponding
graph. . . . . . . . . . . . . . . . . . . . . . .. .. . 9.8 . .
4.4 ( a) Nine arrays with shared spares. (b) The corresponding
generalized bipartite graph. . . . . . . . . . . . . . .. . 99.
4.5 (a) An array with interstitial redundancy. (b) The corre-
sponding generalized bipartite graph ............. 100
4.6 (a) Interstitial array with two types of spares. (b) The
corresponding generalized bipartite graph. 101
4.7 Splitting vertices u, v, and w. . . . . . . . . . . 110
4.8 Network construction for problem 13. ..... 113
4.9 An example of the construction in Theorem 16. 117
List of Tables
2.1 Experimental results for the feasible minimum cover prob-
lem. .. . .. .. 40
2.2 Experimental results. . . . 48
4.1 Experimental results for homogeneous arrays. 106
4.2 Experimental results for homogeneous arrays. 106
4.3 Experimental results for arrays with shared spares. 107
4.4 Experimental results for interstitial arrays with two types
of spares. . . . . 108
4.5 Sixteen sub cases of the general formulation. 109
4.6 Experimental results for problem 13. . . . 113
