ESD in Silicon Integrated Circuits, Second Edition

421 Pages·2002·3.474 MB·English

by  Ajith Amerasekera, Charvaka Duvvury(auth.)

ESDinSiliconIntegratedCircuits,2ndEdition
AjithAmerasekera,CharvakaDuvvury
Copyright(cid:1)c 2002JohnWiley&Sons,Ltd
ISB N s : 0-471-49871-8 (Hardback); 0-470-84605-4 (Electronic)
ESD in Silicon
Integrated Circuits
Second Edition
ESD in Silicon
Integrated Circuits
Second Edition
Ajith Amerasekera
Charvaka Duvvury
TexasInstruments, Inc., USA
With
Warren Anderson
CompaqComputer Corporation,USA
Horst Gieser
Fraunhofer Institute for Reliabilityand
MicrointegrationIZM ATIS, Germany
Sridhar Ramaswamy
TexasInstruments, Inc., USA
Copyright(cid:1)c 2002by JohnWiley&Sons,Ltd.,
BaffinsLane,Chichester,
WestSussexPO191UD,England
Phone[phone]
e-mail(forordersandcustomerserviceenquiries):[email protected]
VisitourHomePageonhttp://www.wileyeurope.comorhttp://www.wiley.com
AllRightsReserved.Nopartofthispublicationmaybereproduced,storedinaretrievalsystemor
transmittedinanyformorbyanymeans,electronic,mechanical,photocopying,recording,scanning
orotherwise,exceptunderthetermsoftheCopyright,DesignsandPatentsAct1988orunderthe
termsofalicenseissuedbytheCopyrightLicensingAgencyLtd.,90TottenhamCourtRoad,London
W1P0LP,UKwithoutthepermissioninwritingofthePublisher.RequeststothePublishershouldbe
addressedtothePermissionsDepartment,JohnWiley&Sons,Ltd.,BaffinsLane,Chichester,West
SussexPO191UD,England,[email protected],orfaxedto([phone].
OtherWileyEditorialOffices
JohnWiley&Sons,Inc.,605ThirdAvenue,
NewYork,NY10158-0012,USA
Jossey-Bass,989MarketStreet,
SanFrancisco,CA94103-1741,USA
WILEY-VCHVerlagGmbH,Pappelallee3,
D-69469Weinheim,Germany
JohnWiley&SonsAustralia,Ltd.,33ParkRoad,
Milton,Queensland4064,Australia
JohnWiley&Sons(Asia)PteLtd.,2ClementiLoop#02-01,
JinXingDistripark,Singapore129809
JohnWiley&SonsCanada,Ltd.,22WorcesterRoad,
Etobicoke,Ontario,CanadaM9W1L1
BritishLibraryCataloguinginPublicationData
AcataloguerecordforthisbookisavailablefromtheBritishLibrary
ISBN0470498718
Typesetin10/12ptTimesbyLaserwordsPrivateLimited,Chennai,India.
PrintedandboundinGreatBritainbyAntonyRoweLtd.,Chippenham,Wiltshire.
Thisbookisprintedonacid-freepaperresponsiblymanufacturedfromsustainableforestry
inwhichatleasttwotreesareplantedforeachoneusedforpaperproduction.
Contents
Preface ix
1 Introduction 1
1.1 Background 1
1.2 The ESD Problem 3
1.3 Protecting Against ESD 4
1.4 Outline of the Book 4
Bibliography 7
2 ESD Phenomenon 8
2.1 Introduction 8
2.2 Electrostatic Voltage 9
2.3 Discharge 11
2.4 ESD Stress Models 12
Bibliography 15
3 Test Methods 17
3.1 Introduction 17
3.2 Human Body Model (HBM) 18
3.3 Machine Model (MM) 27
3.4 Charged Device Model (CDM) 28
3.5 Socket Device Model (SDM) 40
3.6 Metrology, Calibration, Verification 42
3.7 Transmission Line Pulsing (TLP) 47
3.8 Failure Criteria 58
3.9 Summary 60
Bibliography 61
4 Physics and Operation of ESD Protection Circuit Elements 68
4.1 Introduction 68
4.2 Resistors 68
4.3 Diodes 70
vi CONTENTS
4.4 Transistor Operation 77
4.5 Transistor Operation under ESD Conditions 85
4.6 Electrothermal Effects 95
4.7 SCR Operation 98
4.8 Conclusion 101
Bibliography 102
5 ESD Protection Circuit Design Concepts and Strategy 105
5.1 The Qualities of Good ESD Protection 106
5.2 ESD Protection Design Methods 109
5.3 Selecting an ESD Strategy 123
5.4 Summary 124
Bibliography 124
6 Design and Layout Requirements 126
6.1 Introduction 126
6.2 Thick Field Device 127
6.3 nMOS Transistors (FPDs) 132
6.4 Gate-Coupled nMOS (GCNMOS) 138
6.5 Gate Driven nMOS (GDNMOS) 149
6.6 SCR Protection Device 150
6.7 ESD Protection Design Synthesis 155
6.8 Total Input Protection 164
6.9 ESD Protection Using Diode-Based Devices 172
6.10 Power Supply Clamps 176
6.11 Bipolar and BiCMOS Protection Circuits 179
6.12 Summary 183
Bibliography 184
7 Advanced Protection Design 188
7.1 Introduction 188
7.2 PNP-Driven nMOS (PDNMOS) 188
7.3 Substrate Triggered nMOS (STNMOS) 189
7.4 nMOS Triggered nMOS (NTNMOS) 192
7.5 ESD for Mixed-Voltage I/O 200
7.6 CDM Protection 214
7.7 SOI Technology 215
7.8 High-Voltage Transistors 216
7.9 BiCMOS Protection 218
7.10 RF Designs 219
7.11 General I/O Protection Schemes 220
7.12 Design/Layout Errors 221
7.13 Summary 223
Bibliography 224
CONTENTS vii
8 Failure Modes, Reliability Issues, and Case Studies 228
8.1 Introduction 228
8.2 Failure Mode Analysis 229
8.3 Reliability and Performance Considerations 238
8.4 Advanced CMOS Input Protection 239
8.5 Optimizing the Input Protection Scheme 242
8.6 Designs for Special Applications 249
8.7 Process Effects on Input Protection Design 253
8.8 Total IC Chip Protection 255
8.9 Power Bus Protection 256
8.10 Internal Chip ESD Damage 258
8.11 Stress Dependent ESD Behavior 263
8.12 Failure Mode Case Studies 267
8.13 Summary 271
Bibliography 272
9 Influence of Processing on ESD 282
9.1 Introduction 282
9.2 High Current Behavior 284
9.3 Cross Section of a MOS Transistor 287
9.4 Drain-Source Implant Effects 288
9.5 p-Well Effects 293
9.6 n-Well Effects 294
9.7 Epitaxial Layers and Substrates 295
9.8 Gate Oxides 298
9.9 Silicides 300
9.10 Contacts 304
9.11 Interconnect and Metalization 305
9.12 Gate Length Dependencies 306
9.13 Silicon-on-Insulator (SOI) 310
9.14 Bipolar Transistors 312
9.15 Diodes 314
9.16 Resistors 315
9.17 Reliability Trade-Offs 316
9.18 Summary 317
Bibliography 320
10 Device Modeling of High Current Effects 326
10.1 Introduction 326
10.2 The Physics of ESD Damage 327
10.3 Thermal (“Second”) Breakdown 330
10.4 Analytical Models Using the Heat Equation 335
10.5 Electrothermal Device Simulations 339
viii CONTENTS
10.6 Conclusion 344
Bibliography 345
11 Circuit Simulation Basics, Approaches, and Applications 350
11.1 Introduction 350
11.2 Modeling the MOSFET 351
11.3 Modeling Bipolar Junction Transistors 367
11.4 Modeling Diffusion Resistors 371
11.5 Modeling Protection Diodes 375
11.6 Simulation of Protection Circuits 376
11.7 Electrothermal Circuit Simulations 382
11.8 Conclusion 385
Bibliography 389
12 Conclusion 394
12.1 Long-Term Relevance of ESD In ICs 394
12.2 State-of-the-Art for ESD Protection 395
12.3 Current Limitations 396
12.4 Future Issues 398
Bibliography 399
Index 401
Preface
In the seven years since the first edition of this book was completed, Electrostatic
Discharge (ESD) phenomena in integrated circuits (IC) continues to be important
as technologies shrink and the speed and size of the chips increases. The phenom-
enarelatedtoESDeventsinsemiconductordevicestakeplaceoutsidetherealmof
normal device operation. Hence, the physics governing this behavior are not typ-
ically found in general textbooks on semiconductors. Similarly the circuit design
issues involve nonstandard approaches that are not covered in general books on
electronic design. There has been a large amount of work done in the areas of
ESD circuit design and the physics involved, most of which has been published
in a number of papers and conference proceedings. This book covers the state-
of-the-art in circuit design for ESD prevention as well as the device physics, test
methods, and characterization. We also include case studies showing examples of
approaches to solving ESD design problems.
For the second edition, we have completely revised a number of chapters and
broughtotherchaptersuptodatewiththelatestlearning.Thelastsevenyearshave
seen many developments in the understanding of ESD phenomenon and the issues
related to circuit and transistor design, as well as to modeling and simulation.
ThebookisintendedforthoseworkinginthefieldofICcircuitdesignandtran-
sistordevicedesign.Inaddition,thebasicspresentedinthisbookshouldalsoappeal
tograduatestudentsinthefieldofsemiconductorreliabilityanddevice/circuitmod-
eling. As the problems associated with ESD become significant in the IC industry
thedemandforgraduateswithabasicknowledgeofESDphenomenaalsoincreases.
We hope that this book will help students meet the demands of the IC industry in
terms of understanding and approaching ESD problems in semiconductor devices.
There are many companies and research institutes that have made it possible to
understandandsolvethemajorityofESDproblemsinICs.Someofthecompanies
that have been particularly active in recent years are Texas Instruments, Philips
Semiconductors, Lucent, Rockwell, IBM, Motorola, DEC/Compaq, David Sarnoff
Labs, and Intel. Research Institutes that have made significant contributions in
recent years are Sandia National Labs, Clemson University, Stanford University,
the University of California in Berkeley, the University of Western Ontario in
Canada, the University of Illinois at Urbana-Champain, Twente University in The
Netherlands, the Technical University of Munich and the Fraunhofer Institute both
in Germany, and IMEC in Belgium.
Wehavemanypeopletothankfortheircontributionstoourpersonalknowledge
andunderstandinginthisarea.WewouldparticularlyliketothankRobertRountree,
x PREFACE
ThomasPolgreen,andAmitavaChatterjeefortheircontributionsbothatthecircuit
design and at the device level. Ping Yang and William Hunter have provided
excellenttechnicalguidanceduringtheevolutionoftheworkonESD,andwithout
their management support this work would not have been undertaken in the first
place.ManyofourcolleagueshereatTexasInstrumentshavedonethegroundwork,
which has helped us expand our understanding in this area. We are especially
gratefulforthecontributionsofKuen-LongChen,DavidScott,VikasGupta,Mike
Chaine, Karthik Vasanth, Vijay Reddy, Tom Diep, Steve Marum, and Julian Chen,
in this respect. In the area of device physics and modeling, the contributions of
Mi-Chang Chang, Kartikeya Mayaram, Jue-Hsien Chern and Jerold Seitchik have
beeninvaluable.Wehavehadthepleasureofworkingcloselywithmanyacademic
institutions,andwethankProfessorsHenryDomingosatClarksonUniversity,Ken
Goodson,RobertDutton,KaustavBanerjeeatStanfordUniversity,ChenmingHuat
UCBerkeley,ElyseRosenbaumandSteveKangatUniversityofIllinoisatUrbana-
Champain, and Jan Verweij, and Fred Kuper at the University of Twente, for their
collaborationovertheyears.Wegreatlyappreciatethesignificantcontributionsthat
CarlosDiazandSridharRamaswamy(UniversityofIllinois atUrbana-Champain),
KaustavBanerjee(UCBerkeley),XinYiZhang(Stanford),SungtaekJu(Stanford),
and Gianluca Boselli (University of Twente), during their PhD studentships, have
made to our understanding of the many issues related to ESD in silicon integrated
circuits.
Ajith Amerasekera
Charvaka Duvvury
Dallas, November 2001.
ESDinSiliconIntegratedCircuits,2ndEdition
AjithAmerasekera,CharvakaDuvvury
Copyright(cid:1)c 2002JohnWiley&Sons,Ltd
ISBNs:0-471-49871-8(Hardback);0-470-84605-4(Electronic)
Index
Abruptjunction 76,131,133,239, Avalanchebreakdown 70,71,73,75,
249,252,253,288,289,291,292, 76,81,89,90,100,131,133,138,
317 139,141,150,157,158,160,162,
Adiabatic 336,338 236,241,242,250,288,290,298,
AEC 22,24,28,29 299,329,333,350,351,354,357,
Aluminium-silicon 359,364,368,369,373,375,383,
diffusions 304,334 389
Aluminum-silicon 304 region 351
eutectictemperature 334 voltage 71,75,76,90,100,133,
AnalyticalCDM-testing 38 139,141,157,160,236,250,290,
Analyticalmodels 4,335,336,339, 298,354,357,359,364
341,344,375
Anode 73,76,98–100,150,151,157, Backgroundcapacitance 23,34
164,218,240,297,314,315,319, Bakeableleakagecurrent 238
373,374 Ballastresistance 96,283
tocathodespacing 99 Barriermetal 304
Applications 6,25,35,38,39,44,45, Basecharge factor 359
47,57,85,98,136,138,143,144, Basecurrent 77–79,84,86,89,95,
146,153,155–157,162,170,171, 120,175,207,212,282,284,285,
179,183,189,192,215,216, 292,310,327,344,355,369,370,
218–220,223,238,247,249,326, 376,386
350,376,395–397,399 Basetransittime 21,57,80,89,314,
automotive 247 363
industrial 247 Basetransportfactor 79,352,356
special 238 Base-emitterresistance 219
Arsenicimplantation 290 Basicinputprotectionscheme 156
ASIC 377,381 BiCMOS 14,95,126,157,179–184,
cell 381,382 188,218,219,223,327,368,371,
library 377 383,396
Avalanche 11,12,70,71,73–76,81, BiCMOSprotectioncircuits 184
83–86,88–90,95–97,100,101, Bipolar 4,24,48,55,68,77,78,80,
123,131,133,138,139,141,150, 83–86,88–92,95,96,98,101,
152,157–162,164,166,170,171, 126–129,131,133,139,144,155,
180,236,241,242,250,282,284, 179–182,184,202,208,209,215,
285,287,288,290,298,299,311, 216,218,219,223,250,251,257,
313,315,327,329,333,334,339, 282–288,292,295,299,301–303,
340,343–345,350,351,353–357, 307,310–315,317–319,327–329,
359,364,367–370,373,375,382, 344,350–358,361,363,367–369,
383,389 371,382,383,385,386,389,396
conditions 83,85 collectorcurrentinthenpn 77
generated current 11 efficiency 129
generation 11 gaindegradation 94,95,366
multiplication 12 lateral 88,89,127,284,285,355